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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2025 16:03:55.5319 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d05349a1-cf93-4b49-6a33-08ddc9395c56 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9515 Add device tree bindings for Xilinx Versal EDAC for XilSem controller Signed-off-by: Rama devi Veggalam --- Changes in v2: - Changed "xlnx,versal-xilsem-edac" to constant - Removed "compatible: in required section - Removed "|" in description - Removed "items" in compatible - Fixed indentation in examples - Updated title and description --- .../edac/xlnx,versal-xilsem-edac.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml diff --git a/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml b/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml new file mode 100644 index 000000000000..23c1d0557a66 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/xlnx,versal-xilsem-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal Soft Error Mitigation (XilSEM) EDAC + +maintainers: + - Rama Devi Veggalam + +description: + Xilinx Versal Soft Error Mitigation (XilSEM) is part of the + Platform Loader and Manager (PLM) which is loaded into and runs on the + Platform Management Controller (PMC). XilSEM is responsible for reporting + and optionally correcting soft errors in Configuration Memory of Versal. + The memory is scanned by a hardware controller in the Versal Programmable + Logic (PL). During the scan, if the controller detects any error, be it + correctable or uncorrectable, it reports the error to PLM. The XilSEM on PLM + performs the error validation and notifies the errors to user application. + This XilSEM EDAC node is responsible for handling error events received from + XilSEM on PLM and also provides an interface to control scan operations and + fetching the scan status & configuration information. + +properties: + compatible: + const: xlnx,versal-xilsem-edac + + reg: + maxItems: 1 + +required: + - reg + +additionalProperties: false + +examples: + - | + edac@f2014050 { + compatible = "xlnx,versal-xilsem-edac"; + reg = <0xf2014050 0xc4>; + }; -- 2.23.0