[PATCH v1 i2c-master] i2c: mchp-pci1xxxx: Update minimum bus idle time

[Rengarajan S <rengarajan.s@microchip.com>]

The SMBUS controller clock is designed with a 64 MHz clock for the
MCU, while the PCI1xxxx chip assumes a 31.25 MHz baud clock. SMBUS
controller register values are calculated considering 1 unit = 32 ns.
Based on this unit, the BUS_IDLE_MIN register values are updated for
all supported clock frequencies. Setting the MSB of BUS_IDLE_MIN[7:0]
register further scales the minimum bus idle time by a factor of 4.

Fixes: aa874cdfec07 ("i2c: mchp-pci1xxxx: Update Timing registers")
Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
---
 drivers/i2c/busses/i2c-mchp-pci1xxxx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mchp-pci1xxxx.c b/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
index 5ef136c3ecb1..cb9455b38c1d 100644
--- a/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
+++ b/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
@@ -190,9 +190,9 @@
  * Bus Idle Minimum time = BUS_IDLE_MIN[7:0] x Baud_Clock_Period x
  * (BUS_IDLE_MIN_XK_TICKS[7] ? 4,1)
  */
-#define BUS_IDLE_MIN_100K_TICKS		36UL
-#define BUS_IDLE_MIN_400K_TICKS		10UL
-#define BUS_IDLE_MIN_1000K_TICKS	4UL
+#define BUS_IDLE_MIN_100K_TICKS		165
+#define BUS_IDLE_MIN_400K_TICKS		40
+#define BUS_IDLE_MIN_1000K_TICKS	16
 
 /*
  * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out.
-- 
2.25.1