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Additional changes: - remove label at example dts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- V2 resend, add Krzysztof Kozlowski's review by. Change from v1 to v2 - move under interrupt-controller --- .../arm/freescale/fsl,vf610-mscm-ir.txt | 30 --------- .../fsl,vf610-mscm-ir.yaml | 63 +++++++++++++++++++ 2 files changed, 63 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt deleted file mode 100644 index 6dd6f399236d5..0000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt +++ /dev/null @@ -1,30 +0,0 @@ -Freescale Vybrid Miscellaneous System Control - Interrupt Router - -The MSCM IP contains multiple sub modules, this binding describes the second -block of registers which control the interrupt router. The interrupt router -allows to configure the recipient of each peripheral interrupt. Furthermore -it controls the directed processor interrupts. The module is available in all -Vybrid SoC's but is only really useful in dual core configurations (VF6xx -which comes with a Cortex-A5/Cortex-M4 combination). - -Required properties: -- compatible: "fsl,vf610-mscm-ir" -- reg: the register range of the MSCM Interrupt Router -- fsl,cpucfg: The handle to the MSCM CPU configuration node, required - to get the current CPU ID -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: Two cells, interrupt number and cells. - The hardware interrupt number according to interrupt - assignment of the interrupt router is required. - Flags get passed only when using GIC as parent. Flags - encoding as documented by the GIC bindings. - -Example: - mscm_ir: interrupt-controller@40001800 { - compatible = "fsl,vf610-mscm-ir"; - reg = <0x40001800 0x400>; - fsl,cpucfg = <&mscm_cpucfg>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - } diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml new file mode 100644 index 0000000000000..fdc254f8d013c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,vf610-mscm-ir.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Vybrid Miscellaneous System Control - Interrupt Router + +description: + The MSCM IP contains multiple sub modules, this binding describes the second + block of registers which control the interrupt router. The interrupt router + allows to configure the recipient of each peripheral interrupt. Furthermore + it controls the directed processor interrupts. The module is available in all + Vybrid SoC's but is only really useful in dual core configurations (VF6xx + which comes with a Cortex-A5/Cortex-M4 combination). + + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,vf610-mscm-ir + + reg: + maxItems: 1 + + fsl,cpucfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The handle to the MSCM CPU configuration node, required + to get the current CPU ID + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + Two cells, interrupt number and cells. + The hardware interrupt number according to interrupt + assignment of the interrupt router is required. + Flags get passed only when using GIC as parent. Flags + encoding as documented by the GIC bindings. + +required: + - compatible + - reg + - fsl,cpucfg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@40001800 { + compatible = "fsl,vf610-mscm-ir"; + reg = <0x40001800 0x400>; + fsl,cpucfg = <&mscm_cpucfg>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + }; -- 2.34.1