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Fri, 25 Jul 2025 09:56:59 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:8c15:2281:5347:b367]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-458705bcbb7sm61690015e9.18.2025.07.25.09.56.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 09:56:59 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Deepak Gupta Subject: [PATCH v2 0/4] riscv: minor thread_info.cpu improvements Date: Fri, 25 Jul 2025 18:54:08 +0200 Message-ID: <20250725165410.2896641-3-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.50.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hello, I noticed that we give thread_info.cpu two different names in the assembly, load it as a wider type, and store it suboptimally. v2 is split for easy backporting. Thanks. v2: * transform [v1 2/3] into [v2 1-2/4] to simplify backports [Alex] * tested and reviewed by Alex v1: https://lore.kernel.org/lkml/20250722160556.2216925-2-rkrcmar@ventanamicro.com/ Radim Krčmář (4): riscv: use lw when reading int cpu in new_vmalloc_check riscv: use lw when reading int cpu in asm_per_cpu riscv: use TASK_TI_CPU instead of TASK_TI_CPU_NUM riscv: pack rv64 thread_info better arch/riscv/include/asm/asm.h | 2 +- arch/riscv/include/asm/thread_info.h | 2 +- arch/riscv/kernel/asm-offsets.c | 1 - arch/riscv/kernel/entry.S | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) -- 2.50.0