From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6B78213254; Sun, 27 Jul 2025 10:02:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753610523; cv=none; b=uScwBKRbG6FTBC0dv0RR+NKQkx3mHT/VyusOz7QF5hEsJzOf1E8pEB2gJBz63tMo4GiYLP0Alv+K6uSiVqaszeFdf0NNAHbaj2Mp+RFE4btIlkrU9E+skfZUZoxonx+bdhEzrjgdtA1tbU0GgAueoS3p4diM8l5nK5okEi0mdIw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753610523; c=relaxed/simple; bh=ijK+Py6Dx0tvPwLNftNTZxYbg07I+IQK6edrqihy18Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AnfZ6m99hsYSC6M/0PrgODCy3iVD0Bl3sDpPz5gOBxHXpQWpKeHFR+0Lzz7PMbgdWAxm8KBnFScFa5f5JJl9IufUgT1qD85SIoW/q5lEymETMTRZqq/6aDRS4h6Mq/3I/9c0fRraOiDUpp0rXhlONOnlvr/x1B6hl7uHROddaL0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=gwXsKdMk; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="gwXsKdMk" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D5E361038C12A; Sun, 27 Jul 2025 12:01:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1753610519; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=BVpiILTV80CJs+EYpnmSAZ9eYeJRzivliu+/2PyKhfc=; b=gwXsKdMkNODQmItmNnxiJTgFss4VcmUz5XmgcsgAen37/vCqP1TyeLQorEwUVTnDyfteRO +U+gRNsmsVdSjbealGv/TggnMxfr4jZUkDkRCZZyFQVNvdunCfe5vocDE7og5PsdlxKW2B 140L8fjDDKQGUJOvaYs04jHk78mnWE2YX9vQnabYeSwx7BTn5Vgi3lIO68K5OYDAlDhrFf 8JwwKS+prHtGIVgURuv0zJ8Fz7S/Hcd41U5Fh/CEtH/6AwmHqwlUJ/Zmhn4R4SGpQQsat+ 3eNEvk1vsqiDl+04Mb5p5MIylOG/2mH8/ZzUNpFaoVUv3RyX2kq3LSa2Q/B7fA== From: Lukasz Majewski To: Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Richard Cochran , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Stefan Wahren , Simon Horman , Lukasz Majewski , Andrew Lunn Subject: [net-next v17 03/12] ARM: dts: nxp: mxs: Adjust XEA board's DTS to support L2 switch Date: Sun, 27 Jul 2025 12:01:19 +0200 Message-Id: <20250727100128.1411514-4-lukma@denx.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250727100128.1411514-1-lukma@denx.de> References: <20250727100128.1411514-1-lukma@denx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 The description is similar to the one used with the new CPSW driver. Signed-off-by: Lukasz Majewski Reviewed-by: Andrew Lunn Reviewed-by: Stefan Wahren --- Changes for v2: - Remove properties which are common for the imx28(7) SoC - Use mdio properties to perform L2 switch reset (avoid using deprecated properties) Changes for v3: - Replace IRQ_TYPE_EDGE_FALLING with IRQ_TYPE_LEVEL_LOW - Update comment regarding PHY interrupts s/AND/OR/g Changes for v4: - Use GPIO_ACTIVE_LOW instead of 0 in 'reset-gpios' - Replace port@[12] with ethernet-port@[12] Changes for v5: - Add proper multiline comment for IRQs description Changes for v6 - v17: - None --- arch/arm/boot/dts/nxp/mxs/imx28-xea.dts | 56 +++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts index 6c5e6856648a..69032b29d767 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts @@ -5,6 +5,7 @@ */ /dts-v1/; +#include #include "imx28-lwe.dtsi" / { @@ -90,6 +91,61 @@ ®_usb_5v { gpio = <&gpio0 2 0>; }; +ð_switch { + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>, <&mac1_pins_a>; + phy-supply = <®_fec_3v3>; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + mtip_port1: ethernet-port@1 { + reg = <1>; + label = "lan0"; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + }; + + mtip_port2: ethernet-port@2 { + reg = <2>; + label = "lan1"; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + }; + }; + + mdio_sw: mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + reset-delay-us = <25000>; + reset-post-delay-us = <10000>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + smsc,disable-energy-detect; + /* + * Both PHYs (i.e. 0,1) have the same, single GPIO, + * line to handle both, their interrupts (OR'ed) + */ + interrupt-parent = <&gpio4>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + smsc,disable-energy-detect; + interrupt-parent = <&gpio4>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + &spi2_pins_a { fsl,pinmux-ids = < MX28_PAD_SSP2_SCK__SSP2_SCK -- 2.39.5