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[47.55.120.4]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7e643897b24sm431209085a.75.2025.07.29.07.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Jul 2025 07:29:18 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1uglKP-00000000JGf-22cn; Tue, 29 Jul 2025 11:29:17 -0300 Date: Tue, 29 Jul 2025 11:29:17 -0300 From: Jason Gunthorpe To: "Aneesh Kumar K.V" Cc: linux-coco@lists.linux.dev, kvmarm@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, aik@amd.com, lukas@wunner.de, Samuel Ortiz , Xu Yilun , Suzuki K Poulose , Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , Oliver Upton Subject: Re: [RFC PATCH v1 06/38] iommufd: Add and option to request for bar mapping with IORESOURCE_EXCLUSIVE Message-ID: <20250729142917.GF26511@ziepe.ca> References: <20250728135216.48084-1-aneesh.kumar@kernel.org> <20250728135216.48084-7-aneesh.kumar@kernel.org> <20250728140841.GA26511@ziepe.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Jul 29, 2025 at 01:58:54PM +0530, Aneesh Kumar K.V wrote: > Jason Gunthorpe writes: > > > On Mon, Jul 28, 2025 at 07:21:43PM +0530, Aneesh Kumar K.V (Arm) wrote: > >> Signed-off-by: Aneesh Kumar K.V (Arm) > > > > Why would we need this? > > > > I can sort of understand why Intel would need it due to their issues > > with MCE, but ARM shouldn't care either way, should it? > > > > But also why is it an iommufd option? That doesn't seem right.. > > > > Jason > > This is based on our previous discussion https://lore.kernel.org/all/20250606120919.GH19710@nvidia.com I suggested a global option, this is a per-device option, and that especially seems wrong for iommufd. If it is per-device that is vfio, if it is global then vfio can pick it up during the early phases of opening the device. > IIUC, we intend to request the resource in exclusive mode for secure > guests—regardless of whether the platform is Intel or ARM. Could you > help clarify the MCE issue observed on Intel platforms in this context? As I understand it Intel MCEs if the non-secure side ever reads from secure'd address space. So there is alot of emphasis there to ensure there are no CPU mappings. Jason