From: Manikandan Muralidharan <manikandan.m@microchip.com>
To: <broonie@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <nicolas.ferre@microchip.com>,
<alexandre.belloni@bootlin.com>, <claudiu.beznea@tuxon.dev>,
<ryan.wanner@microchip.com>, <tudor.ambarus@linaro.org>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <manikandan.m@microchip.com>
Subject: [PATCH v3 1/3] spi: atmel: simplify MR register update in cs_activate()
Date: Tue, 5 Aug 2025 15:55:08 +0530 [thread overview]
Message-ID: <20250805102510.36507-2-manikandan.m@microchip.com> (raw)
In-Reply-To: <20250805102510.36507-1-manikandan.m@microchip.com>
simplified the MR register configuration by updating only the PCS field
using SPI_BFINS() instead of rewriting the entire register.
Avoids code duplication.
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
---
drivers/spi/spi-atmel.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 89a6b46cd319..409f544d8983 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -397,20 +397,10 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
* on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
*/
spi_writel(as, CSR0, asd->csr);
- if (as->caps.has_wdrbt) {
- spi_writel(as, MR,
- SPI_BF(PCS, ~(0x01 << chip_select))
- | SPI_BIT(WDRBT)
- | SPI_BIT(MODFDIS)
- | SPI_BIT(MSTR));
- } else {
- spi_writel(as, MR,
- SPI_BF(PCS, ~(0x01 << chip_select))
- | SPI_BIT(MODFDIS)
- | SPI_BIT(MSTR));
- }
mr = spi_readl(as, MR);
+ mr = SPI_BFINS(PCS, ~(0x01 << chip_select), mr);
+ spi_writel(as, MR, mr);
/*
* Ensures the clock polarity is valid before we actually
--
2.25.1
next prev parent reply other threads:[~2025-08-05 10:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-05 10:25 [PATCH v3 0/3] spi: atmel: Add GCLK support and simplify MR update Manikandan Muralidharan
2025-08-05 10:25 ` Manikandan Muralidharan [this message]
2025-08-05 10:25 ` [PATCH v3 2/3] spi: dt-bindings: atmel,at91rm9200-spi: Add support for optional 'spi_gclk' clock Manikandan Muralidharan
2025-08-05 18:00 ` Rob Herring
2025-08-05 10:25 ` [PATCH v3 3/3] spi: atmel: Add support for handling GCLK as a clock source Manikandan Muralidharan
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