From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BFAE275847; Tue, 5 Aug 2025 13:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754402143; cv=none; b=dRb1srwbWd06u8CvCubq+v6rU/eMsXpYQ35Gp9lDiXIk5P0+laZqvIhHtrj74kSwe1U72DaNulgFk184iI9X8NCsTKEcB/qY8qnGzL7GAcZ7DlMvu6R327kwvihQfD2LLpL9ATj6nhuiRvcnPXUOHY+L60Scbe65H7zMchJ5iTI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754402143; c=relaxed/simple; bh=JPcbvjRPjjNe9bbbbk11sMxPdeYwCinklYCS9ZsYp2U=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Content-Type; b=SKvD2qQGxZzooyGY48OWyI6INAa8X5jmDGoO7XIu9lgJL+6zvSB29sHPlt8mozOrKywqN0rJM9eYa3hvmNTPhkfxGzgSgseynQI0oEGFCHygEL/vAqWgqCNUwaXwI4odRRQerumnKpr0qkgXPuAchX4f+7VgmklsdMC63lbX56E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nPkAnAf3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nPkAnAf3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754402139; bh=JPcbvjRPjjNe9bbbbk11sMxPdeYwCinklYCS9ZsYp2U=; h=From:To:Cc:Subject:Date:From; b=nPkAnAf3AnmP+5CJ3pdbEsXE+vs+Dgbg1j5iblS/SeGjwcEnJWDmbVaTzROY2tUpM qgYjtKg0Wv1gTDxZWj1w8URCSWLxfZuhSI9HYiDn+t8NdfTgIZsBatu9GuaOGmSspi iZSZ8zO1QZMeuVv9gRhvPOAVDPYOat4BGjPVNRWuhNQ42WcbgD6k35N4JjmeBQWJQ6 m/A/MFfzkU/Z5qv+7GmyiukO82xaWJZcB5DqhIwxgjhOWSXvUrZDCkps+0gwr7UfFy 4/hSiUQMHOO2UKh/sdppRvZpBmLOyGfP1bPQedSsQ3QVjfM9HvlmUki3kfEeOI9zsh 2DjL4LC91ezBA== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:1976:d3fe:e682:e398]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 307A317E0506; Tue, 5 Aug 2025 15:55:38 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH v4 00/27] Add support for MT8196 clock controllers Date: Tue, 5 Aug 2025 15:54:20 +0200 Message-Id: <20250805135447.149231-1-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch series introduces support for the clock controllers on the MediaTek MT8196 platform, following up on an earlier submission[1]. MT8196 uses a hardware voting mechanism to control some of the clock muxes and gates, along with a fence register responsible for tracking PLL and mux gate readiness. The series introduces support for these voting and fence mechanisms, and includes drivers for all clock controllers on the platform. [1] https://lore.kernel.org/all/20250307032942.10447-1-guangjie.song@mediatek.com/ Changes in v4: - Expanded the commit message for the clock controller bindings to include the addition of the hardware voter handle - Extended the description of the mediatek,hardware-voter phandle to explain the limitations of the HWV implementation on MT8196 and justify the use of a custom handle instead of relying on generic APIs Link to v3: https://lore.kernel.org/all/20250624143220.244549-1-laura.nao@collabora.com Laura Nao (27): clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct clk: mediatek: clk-gate: Add ops for gates with HW voter clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro dt-bindings: clock: mediatek: Describe MT8196 clock controllers clk: mediatek: Add MT8196 apmixedsys clock support clk: mediatek: Add MT8196 topckgen clock support clk: mediatek: Add MT8196 topckgen2 clock support clk: mediatek: Add MT8196 vlpckgen clock support clk: mediatek: Add MT8196 peripheral clock support clk: mediatek: Add MT8196 ufssys clock support clk: mediatek: Add MT8196 pextpsys clock support clk: mediatek: Add MT8196 I2C clock support clk: mediatek: Add MT8196 mcu clock support clk: mediatek: Add MT8196 mdpsys clock support clk: mediatek: Add MT8196 mfg clock support clk: mediatek: Add MT8196 disp0 clock support clk: mediatek: Add MT8196 disp1 clock support clk: mediatek: Add MT8196 disp-ao clock support clk: mediatek: Add MT8196 ovl0 clock support clk: mediatek: Add MT8196 ovl1 clock support clk: mediatek: Add MT8196 vdecsys clock support clk: mediatek: Add MT8196 vencsys clock support .../bindings/clock/mediatek,mt8196-clock.yaml | 112 ++ .../clock/mediatek,mt8196-sys-clock.yaml | 107 ++ drivers/clk/mediatek/Kconfig | 71 ++ drivers/clk/mediatek/Makefile | 13 + drivers/clk/mediatek/clk-gate.c | 106 +- drivers/clk/mediatek/clk-gate.h | 3 + drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 203 ++++ drivers/clk/mediatek/clk-mt8196-disp0.c | 169 +++ drivers/clk/mediatek/clk-mt8196-disp1.c | 170 +++ .../clk/mediatek/clk-mt8196-imp_iic_wrap.c | 117 +++ drivers/clk/mediatek/clk-mt8196-mcu.c | 166 +++ drivers/clk/mediatek/clk-mt8196-mdpsys.c | 187 ++++ drivers/clk/mediatek/clk-mt8196-mfg.c | 149 +++ drivers/clk/mediatek/clk-mt8196-ovl0.c | 154 +++ drivers/clk/mediatek/clk-mt8196-ovl1.c | 153 +++ drivers/clk/mediatek/clk-mt8196-peri_ao.c | 144 +++ drivers/clk/mediatek/clk-mt8196-pextp.c | 131 +++ drivers/clk/mediatek/clk-mt8196-topckgen.c | 984 ++++++++++++++++++ drivers/clk/mediatek/clk-mt8196-topckgen2.c | 567 ++++++++++ drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 109 ++ drivers/clk/mediatek/clk-mt8196-vdec.c | 253 +++++ drivers/clk/mediatek/clk-mt8196-vdisp_ao.c | 79 ++ drivers/clk/mediatek/clk-mt8196-venc.c | 235 +++++ drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 726 +++++++++++++ drivers/clk/mediatek/clk-mtk.c | 16 + drivers/clk/mediatek/clk-mtk.h | 23 + drivers/clk/mediatek/clk-mux.c | 119 ++- drivers/clk/mediatek/clk-mux.h | 87 ++ drivers/clk/mediatek/clk-pll.c | 46 +- drivers/clk/mediatek/clk-pll.h | 9 + .../dt-bindings/clock/mediatek,mt8196-clock.h | 802 ++++++++++++++ .../reset/mediatek,mt8196-resets.h | 26 + 32 files changed, 6212 insertions(+), 24 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt8196-disp0.c create mode 100644 drivers/clk/mediatek/clk-mt8196-disp1.c create mode 100644 drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c create mode 100644 drivers/clk/mediatek/clk-mt8196-mcu.c create mode 100644 drivers/clk/mediatek/clk-mt8196-mdpsys.c create mode 100644 drivers/clk/mediatek/clk-mt8196-mfg.c create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl0.c create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl1.c create mode 100644 drivers/clk/mediatek/clk-mt8196-peri_ao.c create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen2.c create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c create mode 100644 drivers/clk/mediatek/clk-mt8196-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c create mode 100644 drivers/clk/mediatek/clk-mt8196-venc.c create mode 100644 drivers/clk/mediatek/clk-mt8196-vlpckgen.c create mode 100644 include/dt-bindings/clock/mediatek,mt8196-clock.h create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h -- 2.39.5