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[47.55.120.4]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-7077cde8d56sm73667086d6.73.2025.08.05.09.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 09:08:53 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1ujKDd-00000001YvV-1cIz; Tue, 05 Aug 2025 13:08:53 -0300 Date: Tue, 5 Aug 2025 13:08:53 -0300 From: Jason Gunthorpe To: Alexey Kardashevskiy Cc: "Aneesh Kumar K.V (Arm)" , linux-coco@lists.linux.dev, kvmarm@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, lukas@wunner.de, Samuel Ortiz , Xu Yilun , Suzuki K Poulose , Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , Oliver Upton Subject: Re: [RFC PATCH v1 04/38] tsm: Support DMA Allocation from private memory Message-ID: <20250805160853.GV26511@ziepe.ca> References: <20250728135216.48084-1-aneesh.kumar@kernel.org> <20250728135216.48084-5-aneesh.kumar@kernel.org> <20250728143318.GD26511@ziepe.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Aug 05, 2025 at 08:22:10PM +1000, Alexey Kardashevskiy wrote: >> static inline dma_addr_t phys_to_dma_direct(struct device *dev, >> phys_addr_t phys) >> { >> if (force_dma_unencrypted(dev)) >> return phys_to_dma_unencrypted(dev, phys); >> return phys_to_dma(dev, phys); On AMD what is the force_dma_unencrypted() for? I thought AMD had only one IOMMU and effectively one S2 mapping. Why does it need to change the phys depending on it being shared or private? > On AMD, T=1 only encrypts the PCIe trafic, when a DMA request hits > the IOMMU, the IOMMU decrypts it and then decides whether to encrypt > it with a memory key: if there is secure vIOMMU - it will do what > Cbit says in the guest IOMMU table (this is in the works) oooor just > always set Cbit without guest vIOMMU (which is a big knob per a > device and this is what my patches do now). AMD doesn't have the split IOMMU design that something like ARM has, so it is bit different.. On ARM the T=1 IOMMU should map the entire CPU address space, so any IOVA with any address should just work. So I'd expect AMD and ARM to be the same here. For the T=0 iommu ARM (I think) will only map the shared pages to the shared IPA alias, so the guest VM has to ensure the shared physical alias is used. Then it sounds like the CPU will sometimes accept the private physical alias, and linus will sometimes prefer the physical alias, for the shared memory too so Linux gets things muddled. IMHO ARM probably should fix this much higher up the stack when it has more information to tell if the phys_addr is actualy the private alias a shared page. > > > + bool tdi_enabled:1; > > > }; > > > > I would give the dev->tdi_enabled a clearer name, maybe > > dev->encrypted_dma_supported ? > > > May be but "_enabled", not "_supported". And, ideally, with vIOMMU, at least AMD won't be needing it. Yes Jason