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From: Sean Christopherson <seanjc@google.com>
To: Sean Christopherson <seanjc@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Borislav Petkov <bp@alien8.de>, Xin Li <xin@zytor.com>
Subject: [PATCH v3 1/6] x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions
Date: Tue,  5 Aug 2025 13:22:19 -0700	[thread overview]
Message-ID: <20250805202224.1475590-2-seanjc@google.com> (raw)
In-Reply-To: <20250805202224.1475590-1-seanjc@google.com>

From: Xin Li <xin@zytor.com>

The immediate form of MSR access instructions are primarily motivated
by performance, not code size: by having the MSR number in an immediate,
it is available *much* earlier in the pipeline, which allows the
hardware much more leeway about how a particular MSR is handled.

Use a scattered CPU feature bit for MSR immediate form instructions.

Suggested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kernel/cpu/scattered.c    | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 286d509f9363..75b43bbe2a6d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -491,6 +491,7 @@
 #define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */
 #define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
 #define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */
+#define X86_FEATURE_MSR_IMM		(21*32+14) /* MSR immediate form instructions */
 
 /*
  * BUG word(s)
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index b4a1f6732a3a..5fe19bbe538e 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = {
 	{ X86_FEATURE_APERFMPERF,		CPUID_ECX,  0, 0x00000006, 0 },
 	{ X86_FEATURE_EPB,			CPUID_ECX,  3, 0x00000006, 0 },
 	{ X86_FEATURE_INTEL_PPIN,		CPUID_EBX,  0, 0x00000007, 1 },
+	{ X86_FEATURE_MSR_IMM,			CPUID_ECX,  5, 0x00000007, 1 },
 	{ X86_FEATURE_APX,			CPUID_EDX, 21, 0x00000007, 1 },
 	{ X86_FEATURE_RRSBA_CTRL,		CPUID_EDX,  2, 0x00000007, 2 },
 	{ X86_FEATURE_BHI_CTRL,			CPUID_EDX,  4, 0x00000007, 2 },
-- 
2.50.1.565.gc32cd1483b-goog


  reply	other threads:[~2025-08-05 20:22 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-05 20:22 [PATCH v3 0/6] KVM: VMX: Handle the immediate form of MSR instructions Sean Christopherson
2025-08-05 20:22 ` Sean Christopherson [this message]
2025-08-05 20:22 ` [PATCH v3 2/6] KVM: x86: Rename local "ecx" variables to "msr" and "pmc" as appropriate Sean Christopherson
2025-08-06 15:42   ` Xin Li
2025-08-05 20:22 ` [PATCH v3 3/6] KVM: x86: Rename handle_fastpath_set_msr_irqoff() to handle_fastpath_wrmsr() Sean Christopherson
2025-08-06 15:48   ` Xin Li
2025-08-05 20:22 ` [PATCH v3 4/6] KVM: x86: Add support for RDMSR/WRMSRNS w/ immediate on Intel Sean Christopherson
2025-09-01  4:13   ` Xiaoyao Li
2025-09-01  6:34     ` Binbin Wu
2025-09-01  7:04       ` Xin Li
2025-09-01  7:22         ` Xiaoyao Li
2025-09-02 14:50           ` Sean Christopherson
2025-09-02 15:46             ` Xin Li
2025-09-03  4:43             ` Xiaoyao Li
2025-09-18 18:33               ` Sean Christopherson
2025-08-05 20:22 ` [PATCH v3 5/6] KVM: VMX: Support the immediate form of WRMSRNS in the VM-Exit fastpath Sean Christopherson
2025-08-05 20:22 ` [PATCH v3 6/6] KVM: x86: Advertise support for the immediate form of MSR instructions Sean Christopherson
2025-08-06 15:38 ` [PATCH v3 0/6] KVM: VMX: Handle " Xin Li
2025-08-19 23:12 ` Sean Christopherson

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