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Wed, 06 Aug 2025 06:38:27 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([185.144.39.75]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a21c10asm1113170666b.116.2025.08.06.06.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 06:38:27 -0700 (PDT) From: Rick Wertenbroek To: Cc: rick.wertenbroek@heig-vd.ch, dlemoal@kernel.org, alberto.dassatti@heig-vd.ch, Rick Wertenbroek , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] phy: rockchip-snps-pcie3: add support for rockchip,phy-ref-use-pad Date: Wed, 6 Aug 2025 15:38:20 +0200 Message-Id: <20250806133824.525871-1-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the possibility for the RK3588 PCIe PHYs to use an internal clock instead of a clock provided on a pin of the device. This allows boards that don't have a PCIe clock connected to the reference pad to still function in separate clock mode by using an internal reference clock for the PCIe PHYs. This was tested with a CM3588 compute module on a custom PCB. Without the new option, the default behaviour (PHYs using external pad for clock) is applied, to keep compatibility with existing device trees. Differences from V1 [1] : - Documented the phy-ref-use-pad option in the DT bindings. - Documented the extra optional differential clocks for the PHYs in the DT bindings. [1] https://lore.kernel.org/all/20250715105820.4037272-1-rick.wertenbroek@gmail.com/ Rick Wertenbroek (3): dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks phy: rockchip-snps-pcie3: add support for rockchip,phy-ref-use-pad dt-bindings: phy: rockchip,pcie3-phy: add rockchip,phy-ref-use-pad .../bindings/phy/rockchip,pcie3-phy.yaml | 21 ++++++++++-- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 32 +++++++++++++++++++ 2 files changed, 50 insertions(+), 3 deletions(-) -- 2.25.1