From: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
To: <linux-kernel@vger.kernel.org>
Cc: <bp@alien8.de>, <tglx@linutronix.de>, <mingo@redhat.com>,
<dave.hansen@linux.intel.com>, <Thomas.Lendacky@amd.com>,
<nikunj@amd.com>, <Santosh.Shukla@amd.com>,
<Vasant.Hegde@amd.com>, <Suravee.Suthikulpanit@amd.com>,
<David.Kaplan@amd.com>, <x86@kernel.org>, <hpa@zytor.com>,
<peterz@infradead.org>, <seanjc@google.com>,
<pbonzini@redhat.com>, <kvm@vger.kernel.org>,
<kirill.shutemov@linux.intel.com>, <huibo.wang@amd.com>,
<naveen.rao@amd.com>, <francescolavra.fl@gmail.com>,
<tiala@microsoft.com>
Subject: [PATCH v9 15/18] x86/apic: Add kexec support for Secure AVIC
Date: Mon, 11 Aug 2025 15:14:41 +0530 [thread overview]
Message-ID: <20250811094444.203161-16-Neeraj.Upadhyay@amd.com> (raw)
In-Reply-To: <20250811094444.203161-1-Neeraj.Upadhyay@amd.com>
Add a apic->teardown() callback to disable Secure AVIC before
rebooting into the new kernel. This ensures that the new
kernel does not access the old APIC backing page which was
allocated by the previous kernel. Such accesses can happen
if there are any APIC accesses done during guest boot before
Secure AVIC driver probe is done by the new kernel (as Secure
AVIC would have remained enabled in the Secure AVIC control
msr).
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
---
Changes since v8:
- No change.
arch/x86/coco/sev/core.c | 23 +++++++++++++++++++++++
arch/x86/include/asm/apic.h | 1 +
arch/x86/include/asm/sev.h | 2 ++
arch/x86/kernel/apic/apic.c | 3 +++
arch/x86/kernel/apic/x2apic_savic.c | 8 ++++++++
5 files changed, 37 insertions(+)
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index d7c53b3eeaa9..da7fc7913a00 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -1164,6 +1164,29 @@ enum es_result savic_register_gpa(u64 gpa)
return res;
}
+enum es_result savic_unregister_gpa(u64 *gpa)
+{
+ struct ghcb_state state;
+ struct es_em_ctxt ctxt;
+ enum es_result res;
+ struct ghcb *ghcb;
+
+ guard(irqsave)();
+
+ ghcb = __sev_get_ghcb(&state);
+ vc_ghcb_invalidate(ghcb);
+
+ ghcb_set_rax(ghcb, SVM_VMGEXIT_SAVIC_SELF_GPA);
+ res = sev_es_ghcb_hv_call(ghcb, &ctxt, SVM_VMGEXIT_SAVIC,
+ SVM_VMGEXIT_SAVIC_UNREGISTER_GPA, 0);
+ if (gpa && res == ES_OK)
+ *gpa = ghcb->save.rbx;
+
+ __sev_put_ghcb(&state);
+
+ return res;
+}
+
static void snp_register_per_cpu_ghcb(void)
{
struct sev_es_runtime_data *data;
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 0683318470be..a26e66d66444 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -306,6 +306,7 @@ struct apic {
/* Probe, setup and smpboot functions */
int (*probe)(void);
void (*setup)(void);
+ void (*teardown)(void);
int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
void (*init_apic_ldr)(void);
diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h
index d10ca66aa684..35877c32b528 100644
--- a/arch/x86/include/asm/sev.h
+++ b/arch/x86/include/asm/sev.h
@@ -534,6 +534,7 @@ int snp_svsm_vtpm_send_command(u8 *buffer);
void __init snp_secure_tsc_prepare(void);
void __init snp_secure_tsc_init(void);
enum es_result savic_register_gpa(u64 gpa);
+enum es_result savic_unregister_gpa(u64 *gpa);
u64 savic_ghcb_msr_read(u32 reg);
void savic_ghcb_msr_write(u32 reg, u64 value);
@@ -609,6 +610,7 @@ static inline int snp_svsm_vtpm_send_command(u8 *buffer) { return -ENODEV; }
static inline void __init snp_secure_tsc_prepare(void) { }
static inline void __init snp_secure_tsc_init(void) { }
static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUPPORTED; }
+static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UNSUPPORTED; }
static inline void savic_ghcb_msr_write(u32 reg, u64 value) { }
static inline u64 savic_ghcb_msr_read(u32 reg) { return 0; }
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 69b1084da8f4..badd6a42bced 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1170,6 +1170,9 @@ void disable_local_APIC(void)
if (!apic_accessible())
return;
+ if (apic->teardown)
+ apic->teardown();
+
apic_soft_disable();
#ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index bef77283dd43..71775d6d8fbe 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -326,6 +326,13 @@ static void savic_eoi(void)
}
}
+static void savic_teardown(void)
+{
+ /* Disable Secure AVIC */
+ native_wrmsr(MSR_AMD64_SECURE_AVIC_CONTROL, 0, 0);
+ savic_unregister_gpa(NULL);
+}
+
static void savic_setup(void)
{
void *ap = this_cpu_ptr(secure_avic_page);
@@ -380,6 +387,7 @@ static struct apic apic_x2apic_savic __ro_after_init = {
.probe = savic_probe,
.acpi_madt_oem_check = savic_acpi_madt_oem_check,
.setup = savic_setup,
+ .teardown = savic_teardown,
.dest_mode_logical = false,
--
2.34.1
next prev parent reply other threads:[~2025-08-11 9:50 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-11 9:44 [PATCH v9 00/18] AMD: Add Secure AVIC Guest Support Neeraj Upadhyay
2025-08-11 9:44 ` [PATCH v9 01/18] x86/apic: Add new driver for Secure AVIC Neeraj Upadhyay
2025-08-11 9:44 ` [PATCH v9 02/18] x86/apic: Initialize Secure AVIC APIC backing page Neeraj Upadhyay
2025-08-15 10:25 ` Borislav Petkov
2025-08-15 13:16 ` Upadhyay, Neeraj
2025-08-15 21:05 ` Borislav Petkov
2025-08-11 9:44 ` [PATCH v9 03/18] x86/apic: Populate .read()/.write() callbacks of Secure AVIC driver Neeraj Upadhyay
2025-08-18 11:26 ` Borislav Petkov
2025-08-19 4:15 ` Upadhyay, Neeraj
2025-08-19 14:32 ` Borislav Petkov
2025-08-20 3:33 ` Upadhyay, Neeraj
2025-08-11 9:44 ` [PATCH v9 04/18] x86/apic: Initialize APIC ID for Secure AVIC Neeraj Upadhyay
2025-08-19 21:53 ` Borislav Petkov
2025-08-20 3:34 ` Upadhyay, Neeraj
2025-08-11 9:44 ` [PATCH v9 05/18] x86/apic: Add update_vector() callback for apic drivers Neeraj Upadhyay
2025-08-19 21:59 ` Borislav Petkov
2025-08-20 3:36 ` Upadhyay, Neeraj
2025-08-25 14:49 ` Borislav Petkov
2025-08-26 4:06 ` Upadhyay, Neeraj
2025-08-26 13:25 ` Borislav Petkov
2025-08-11 9:44 ` [PATCH v9 06/18] x86/apic: Add update_vector() callback for Secure AVIC Neeraj Upadhyay
2025-08-11 9:44 ` [PATCH v9 07/18] x86/apic: Add support to send IPI " Neeraj Upadhyay
2025-08-20 15:46 ` Borislav Petkov
2025-08-21 5:27 ` Upadhyay, Neeraj
2025-08-22 17:14 ` Borislav Petkov
2025-08-23 4:20 ` Upadhyay, Neeraj
2025-08-11 9:44 ` [PATCH v9 08/18] x86/apic: Support LAPIC timer " Neeraj Upadhyay
2025-08-11 9:44 ` [PATCH v9 09/18] x86/sev: Initialize VGIF for secondary VCPUs " Neeraj Upadhyay
2025-08-22 17:28 ` Borislav Petkov
2025-08-25 6:25 ` Upadhyay, Neeraj
2025-08-25 14:53 ` Borislav Petkov
2025-08-11 9:44 ` [PATCH v9 10/18] x86/apic: Add support to send NMI IPI " Neeraj Upadhyay
2025-08-25 15:06 ` Borislav Petkov
2025-08-11 9:44 ` [PATCH v9 11/18] x86/apic: Allow NMI to be injected from hypervisor " Neeraj Upadhyay
2025-08-25 15:20 ` Borislav Petkov
2025-08-11 9:44 ` [PATCH v9 12/18] x86/sev: Enable NMI support " Neeraj Upadhyay
2025-08-11 9:44 ` [PATCH v9 13/18] x86/apic: Read and write LVT* APIC registers from HV for SAVIC guests Neeraj Upadhyay
2025-08-11 9:44 ` [PATCH v9 14/18] x86/apic: Handle EOI writes for Secure AVIC guests Neeraj Upadhyay
2025-08-11 9:44 ` Neeraj Upadhyay [this message]
2025-08-11 9:44 ` [PATCH v9 16/18] x86/apic: Enable Secure AVIC in Control MSR Neeraj Upadhyay
2025-08-25 15:54 ` Borislav Petkov
2025-08-11 9:44 ` [PATCH v9 17/18] x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC guests Neeraj Upadhyay
2025-08-25 16:28 ` Borislav Petkov
2025-08-11 9:44 ` [PATCH v9 18/18] x86/sev: Indicate SEV-SNP guest supports Secure AVIC Neeraj Upadhyay
2025-08-25 16:02 ` [PATCH v9 00/18] AMD: Add Secure AVIC Guest Support Borislav Petkov
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