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(146725694.box.freepro.com. [130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e5853104sm271557715e9.8.2025.08.11.15.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 15:30:54 -0700 (PDT) From: Daniel Lezcano To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi.Procopciuc@nxp.com, s32@nxp.com Subject: [PATCH v2 0/2] Add the s32g2 and s32g3 FTM PWM support Date: Tue, 12 Aug 2025 00:30:38 +0200 Message-ID: <20250811223044.3087090-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The NXP Automotive platform s32g2 and s32g3 have on their board a FlexTimer (FTM) dedicated for the PWM. The same IP is found on the Freescale Vybrid Family and the i.MX8 SoCs. However, there is a small difference with some registers not available on the s32g2/3 and 6 channels instead of 8. These two patches provide the DT bindings for the s32g2/3 compatible strings and the code to deal with the FTM difference. Changelog: v2: - Merged the two booleans for the regmap holes check - Clarified why this is needed in the changelog v1: - Initial post Daniel Lezcano (1): dt: bindings: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3 Ghennadi Procopciuc (1): pwm: Add the S32G support in the Freescale FTM driver .../bindings/pwm/fsl,vf610-ftm-pwm.yaml | 11 ++++-- drivers/pwm/pwm-fsl-ftm.c | 35 +++++++++++++++++-- 2 files changed, 41 insertions(+), 5 deletions(-) -- 2.43.0