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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-243086849b3sm1915345ad.175.2025.08.12.01.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 01:37:37 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Yuanfang Zhang , Mao Jinlong , Jie Gan , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 0/9] coresight: ctcu: Enable byte-cntr function for TMC ETR Date: Tue, 12 Aug 2025 16:37:22 +0800 Message-Id: <20250812083731.549-1-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA3NCBTYWx0ZWRfX/uNxOMZzp9S3 gN+8PJulHi0ueGY9GYl0NXWTCSzy1pS4IfduSVnJfHLeNjS62S6XNQxXNI7pVM53PuZQ5W9SrYU OO5WUX0ib9r1zVEiCP/7klzn/1cXvgcBqrUn1Asgh4x3QzGYH1Mv2fYhIUYKNWaIQ15IUM1pPi2 lxNX+bmsUB0LIa1rgFc8Ig9uRYK80WrSzmZQso/MFu5fQfYYnfLdO9uwUALh3U1Rvj9cSX2N1nM i2vPvF/mLyQOJUTtsdCDtxUQFEmM8fXIAAinaR72cdqV5tVZC0HLHFNi8w4TheVwJPGbe8G3IWO YYLLMlOvNNSr9UetH8pMqSsHzIbP1B3ZcXrjIfZa6Q/lkYGLjiLXOXz7vp9pISXWHnLpl6zlvP1 35RsWdT6 X-Proofpoint-GUID: w_rYvgQoEdION7o-Uv6tkjZcW7QR9vi6 X-Authority-Analysis: v=2.4 cv=TJFFS0la c=1 sm=1 tr=0 ts=689afd53 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=4JJaRIKzVo7dG1xzKtwA:9 a=bFCP_H2QrGi7Okbo017w:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: w_rYvgQoEdION7o-Uv6tkjZcW7QR9vi6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_04,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110074 The byte-cntr function provided by the CTCU device is used to count the trace data entering the ETR. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions. Based on this concept, the irq_cnt can be used to determine whether the etr_buf is full. The ETR device will be disabled when the active etr_buf is nearly full or a timeout occurs. The nearly full buffer will be switched to background after synced. A new buffer will be picked from the etr_buf_list, then restart the ETR device. The byte-cntr reading functions can access data from the synced and deactivated buffer, transferring trace data from the etr_buf to userspace without stopping the ETR device. The byte-cntr read operation has integrated with the file node tmc_etr, for example: /dev/tmc_etr0 /dev/tmc_etr1 There are two scenarios for the tmc_etr file node with byte-cntr function: 1. BYTECNTRVAL register is configured and byte-cntr is enabled -> byte-cntr read 2. BYTECNTRVAL register is reset or byte-cntr is disabled -> original behavior Shell commands to enable byte-cntr reading for etr0: echo 0x10000 > /sys/bus/coresight/devices/ctcu0/irq_threshold echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink echo 1 > /sys/bus/coresight/devices/etm0/enable_source cat /dev/tmc_etr0 Enable both ETR0 and ETR1: echo 0x10000 0x10000 > /sys/bus/coresight/devices/ctcu0/irq_threshold Reset the BYTECNTR register for etr0: echo 0 > /sys/bus/coresight/devices/ctcu0/irq_threshold Changes in V5: 1. Add Mike's reviewed-by tag for patchset 1,2,5. 2. Remove the function pointer added to helper_ops according to Mike's comment, it also results the patchset has been removed. 3. Optimizing the paired create/clean functions for etr_buf_list. 4. Remove the unneeded parameter "reading" from the etr_buf_node. Link to V4 - https://lore.kernel.org/all/20250725100806.1157-1-jie.gan@oss.qualcomm.com/ Changes in V4: 1. Rename the function to coresight_get_in_port_dest regarding to Mike's comment (patch 1/10). 2. Add lock to protect the connections regarding to Mike's comment (patch 2/10). 3. Move all byte-cntr functions to coresight-ctcu-byte-cntr file. 4. Add tmc_read_ops to wrap all read operations for TMC device. 5. Add a function in helper_ops to check whether the byte-cntr is enabkled. 6. Call byte-cntr's read_ops if byte-cntr is enabled when reading data from the sysfs node. Link to V3 resend - https://lore.kernel.org/all/20250714063109.591-1-jie.gan@oss.qualcomm.com/ Changes in V3 resend: 1. rebased on next-20250711. Link to V3 - https://lore.kernel.org/all/20250624060438.7469-1-jie.gan@oss.qualcomm.com/ Changes in V3: 1. The previous solution has been deprecated. 2. Add a etr_buf_list to manage allcated etr buffers. 3. Add a logic to switch buffer for ETR. 4. Add read functions to read trace data from synced etr buffer. Link to V2 - https://lore.kernel.org/all/20250410013330.3609482-1-jie.gan@oss.qualcomm.com/ Changes in V2: 1. Removed the independent file node /dev/byte_cntr. 2. Integrated the byte-cntr's file operations with current ETR file node. 3. Optimized the driver code of the CTCU that associated with byte-cntr. 4. Add kernel document for the export API tmc_etr_get_rwp_offset. 5. Optimized the way to read the rwp_offset according to Mike's suggestion. 6. Removed the dependency of the dts patch. Link to V1 - https://lore.kernel.org/all/20250310090407.2069489-1-quic_jiegan@quicinc.com/ Jie Gan (9): coresight: core: Refactoring ctcu_get_active_port and make it generic coresight: core: add a new API to retrieve the helper device coresight: tmc: add etr_buf_list to store allocated etr_buf coresight: tmc: add create/clean functions for etr_buf_list coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations dt-bindings: arm: add an interrupt property for Coresight CTCU coresight: ctcu: enable byte-cntr for TMC ETR devices coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops arm64: dts: qcom: sa8775p: Add interrupts to CTCU device .../testing/sysfs-bus-coresight-devices-ctcu | 5 + .../bindings/arm/qcom,coresight-ctcu.yaml | 17 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 + drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 59 +++ .../coresight/coresight-ctcu-byte-cntr.c | 368 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 108 +++-- drivers/hwtracing/coresight/coresight-ctcu.h | 62 ++- drivers/hwtracing/coresight/coresight-priv.h | 4 + .../hwtracing/coresight/coresight-tmc-core.c | 104 +++-- .../hwtracing/coresight/coresight-tmc-etr.c | 110 ++++++ drivers/hwtracing/coresight/coresight-tmc.h | 39 ++ 12 files changed, 824 insertions(+), 59 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c -- 2.34.1