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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Alim Akhtar , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-pm@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-samsung-soc@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-kernel@vger.kernel.org (open list), llvm@lists.linux.dev (open list:CLANG/LLVM BUILD SUPPORT:Keyword:\b(?i:clang|llvm)\b) Cc: Anand Moon , Mateusz Majewski Subject: [PATCH v7 0/7] Exynos Thermal code improvement Date: Wed, 13 Aug 2025 18:39:44 +0530 Message-ID: <20250813131007.343402-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi All, This patch series is a rework of my previous patch series [1], where the code changes were not adequately justified. In this new series, I have improved the commit subject and commit message to better explain the changes. v7: Integrated my RFC patch which improves the IRQ framework for all the SoC link below. [6] https://lore.kernel.org/all/20250616163831.8138-1-linux.amoon@gmail.com/ v6: Add new patch to use devm_clk_get_enabled and Fix few typo in subject as suggested by Daniel. v5: Drop the guard mutex patch v4: Tried to address Lukasz review comments. I dont have any Arm64 device the test and verify Tested on 32 bit Arch Odroid U3 amd XU4 SoC boards. Build with clang with W=1 enable. Please sare the feedback on this. [5] https://lore.kernel.org/all/20250430123306.15072-1-linux.amoon@gmail.com/ [4] https://lore.kernel.org/all/20250410063754.5483-2-linux.amoon@gmail.com/ [3] https://lore.kernel.org/all/20250310143450.8276-2-linux.amoon@gmail.com/ [2] https://lore.kernel.org/all/20250216195850.5352-2-linux.amoon@gmail.com/ [1] https://lore.kernel.org/all/20220515064126.1424-1-linux.amoon@gmail.com/ [0] https://lore.kernel.org/lkml/CANAwSgS=08fVsqn95WHzSF71WTTyD2-=K2C6-BEz0tY0t6A1-g@mail.gmail.com/T/#m77e57120d230d57f34c29e1422d7fc5f5587ac30 Thanks -Anand Anand Moon (7): thermal/drivers/exynos: Refactor clk_sec initialization inside SOC-specific case thermal/drivers/exynos: Use devm_clk_get_enabled() helpers thermal/drivers/exynos: Remove redundant IS_ERR() checks for clk_sec clock thermal/drivers/exynos: Fixed the efuse min max value for exynos5422 thermal/drivers/exynos: Remove unused base_second mapping and references thermal/drivers/exynos: Handle temperature threshold IRQs with SoC-specific mapping thermal/drivers/exynos: Refactor IRQ clear logic using SoC-specific config drivers/thermal/samsung/exynos_tmu.c | 279 ++++++++++++++++----------- 1 file changed, 163 insertions(+), 116 deletions(-) base-commit: 8742b2d8935f476449ef37e263bc4da3295c7b58 -- 2.50.1