From: Rob Herring <robh@kernel.org>
To: Yao Zi <ziyao@disroot.org>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Huacai Chen <chenhuacai@kernel.org>,
WANG Xuerui <kernel@xen0n.name>,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, loongarch@lists.linux.dev,
Mingcong Bai <jeffbai@aosc.io>,
Kexy Biscuit <kexybiscuit@aosc.io>
Subject: Re: [PATCH 1/3] dt-binding: pinctrl: Document Loongson 2K0300 pin controller
Date: Mon, 18 Aug 2025 12:58:27 -0500 [thread overview]
Message-ID: <20250818175827.GA1507697-robh@kernel.org> (raw)
In-Reply-To: <20250811163749.47028-3-ziyao@disroot.org>
On Mon, Aug 11, 2025 at 04:37:48PM +0000, Yao Zi wrote:
> The pincontroller integarted in Loongson 2K0300 is able to configure
> function multiplexing for all the pins. It could also configure drive
> strength on basis of functions, which means all pins set to the same
> function share drive-strength setting. Drive-strength configuration
> isn't available for all functions, either.
>
> This binding utilizes two levels of subnodes, where the outer represents
> function and the inner represents groups. Drive-strength is allowed in
> the outer since it's shared among all groups configured to the function.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> .../pinctrl/loongson,ls2k0300-pinctrl.yaml | 92 +++++++++++++++++++
> MAINTAINERS | 6 ++
> 2 files changed, 98 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/loongson,ls2k0300-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/loongson,ls2k0300-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/loongson,ls2k0300-pinctrl.yaml
> new file mode 100644
> index 000000000000..cbd74cb45342
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/loongson,ls2k0300-pinctrl.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/loongson,ls2k0300-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson-2K0300 SoC Pinctrl Controller
> +
> +maintainers:
> + - Yao Zi <ziyao@disroot.org>
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +properties:
> + compatible:
> + const: loongson,ls2k0300-pinctrl
> +
> + reg:
> + items:
> + - description: Pin function-multiplexing configuration registers
> + - description: Pin drive-strength configuration registers
> +
> + reg-names:
> + items:
> + - const: mux
> + - const: drive
> +
> +patternProperties:
> + '^func-':
> + type: object
> +
> + $ref: pincfg-node.yaml#
> +
> + properties:
> + drive-strength:
> + description:
> + Maximum sink or source current as defined in pincfg-node.yaml. Note
> + that drive strength could only be configured on function basis, i.e.,
> + all pins multiplexed to the same function share the same
> + configuration.
> +
> + This could only be configured for several functions, including jtag,
> + dvo, uart, gmac, sdio, spi, i2s, timer, usb and emmc.
> + enum: [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]
How do you know what pin this drive strength corresponds to without any
other properties? Node names generally aren't important, so you
shouldn't be using that.
> +
> + additionalProperties: false
> +
> + patternProperties:
> + '-pins$':
> + type: object
> + $ref: pinmux-node.yaml#
Generally the pin config and muxing are in 1 node if you can control
both.
> +
> + properties:
> + pinmux:
> + description:
> + Integer array, represents GPIO pin number and multiplexing
> + setting. Configuration for each pin takes one cell. The pin
> + number locates at the high 24 bits, and the setting locates at
> + the low 8 bits.
> +
> + additionalProperties: false
> +
> + required:
> + - pinmux
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pinctrl@1fe00420 {
> + compatible = "loongson,ls2k0300-pinctrl";
> + reg = <0x16000490 0x20>, <0x16000110 0x4>;
> + reg-names = "mux", "drive";
> +
> + func-uart {
> + drive-strength = <2>;
> +
> + uart0-pins {
> + pinmux = <((40 << 8) | 0x3)>, <((41 << 8) | 0x3)>;
> + };
> +
> + uart1_pins: uart1-pins {
> + pinmux = <((42 << 8) | 0x3)>, <((43 << 8) | 0x3)>;
> + };
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7960e65d7dfc..dd50571b4072 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14414,6 +14414,12 @@ S: Maintained
> F: Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml
> F: drivers/thermal/loongson2_thermal.c
>
> +LOONGSON-2K0300 SOC PINCTRL DRIVER
> +M: Yao Zi <ziyao@disroot.org>
> +L: linux-gpio@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/pinctrl/loongson,ls2k0300-pinctrl.yaml
> +
> LOONGSON EDAC DRIVER
> M: Zhao Qunqin <zhaoqunqin@loongson.cn>
> L: linux-edac@vger.kernel.org
> --
> 2.50.1
>
next prev parent reply other threads:[~2025-08-18 17:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-11 16:37 [PATCH 0/3] Support pinctrl for Loongson 2K0300 SoC Yao Zi
2025-08-11 16:37 ` [PATCH 1/3] dt-binding: pinctrl: Document Loongson 2K0300 pin controller Yao Zi
2025-08-18 17:58 ` Rob Herring [this message]
2025-08-19 11:37 ` Yao Zi
2025-09-12 8:42 ` Yao Zi
2025-10-10 22:05 ` Rob Herring
2025-10-13 22:48 ` Linus Walleij
2025-10-14 2:23 ` Yao Zi
2025-10-14 10:38 ` Linus Walleij
2025-08-11 16:37 ` [PATCH 2/3] pinctrl: ls2k0300: Support Loongson 2K0300 SoC Yao Zi
2025-08-14 3:15 ` Yao Zi
2025-08-19 10:02 ` Linus Walleij
2025-08-19 12:40 ` Yao Zi
2025-08-21 11:27 ` Linus Walleij
2025-08-11 16:37 ` [PATCH 3/3] LoongArch: dts: Add pinctrl configuration for Loongson 2K0300 Yao Zi
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