From: Mateusz Majewski <m.majewski2@samsung.com>
To: linux.amoon@gmail.com
Cc: alim.akhtar@samsung.com, bzolnier@gmail.com,
daniel.lezcano@linaro.org, justinstitt@google.com,
krzk@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
linux-samsung-soc@vger.kernel.org, llvm@lists.linux.dev,
lukasz.luba@arm.com, m.majewski2@samsung.com, morbo@google.com,
nathan@kernel.org, nick.desaulniers+lkml@gmail.com,
rafael@kernel.org, rui.zhang@intel.com
Subject: Re: [PATCH v7 6/7] thermal/drivers/exynos: Handle temperature threshold IRQs with SoC-specific mapping
Date: Tue, 19 Aug 2025 15:17:04 +0200 [thread overview]
Message-ID: <20250819131704.19780-1-m.majewski2@samsung.com> (raw)
In-Reply-To: <20250813131007.343402-7-linux.amoon@gmail.com>
Hello :)
> +/* Map Rise and Falling edges for IRQ Clean */
> +struct tmu_irq_map {
> + u32 fall[3];
> + u32 rise[3];
> +};
Hmm, we can probably get away with less interrupts. We actually only
enable one fall interrupt in tmu_set_low_temp and one rise interrupt in
tmu_set_high_temp.
Regarding tmu_set_crit_temp, on SoCs that have hardware thermal tripping
there is nothing to clear. On others we will reboot immediately anyway,
though maybe there is nothing wrong with clearing the interrupt
beforehand? Regardless of this, there is only a rise critical
temperature interrupt, we never set a matching fall interrupt.
Maybe it would also be good to add a bool to this struct containing
information about whether a fall interrupt is in use, and reuse
the same logic for 4210?
(Nitpick: I am not a native speaker of English, but I think "clean" and
"clear" have slightly different meanings, and the rest of the code
consistently uses "clear", so it would be worthwhile to also use "clear"
here.)
> + /* Set SoC-specific interrupt bit mappings */
> + switch (data->soc) {
> + case SOC_ARCH_EXYNOS3250:
> + case SOC_ARCH_EXYNOS4412:
> + case SOC_ARCH_EXYNOS5250:
> + case SOC_ARCH_EXYNOS5260:
> + irq_map.fall[2] = BIT(20);
> + irq_map.fall[1] = BIT(16);
> + irq_map.fall[0] = BIT(12);
> + irq_map.rise[2] = BIT(8);
> + irq_map.rise[1] = BIT(4);
> + irq_map.rise[0] = BIT(0);
> + break;
> + case SOC_ARCH_EXYNOS5420:
> + case SOC_ARCH_EXYNOS5420_TRIMINFO:
> + irq_map.fall[2] = BIT(24);
> + irq_map.fall[1] = BIT(20);
> + irq_map.fall[0] = BIT(16);
> + irq_map.rise[2] = BIT(8);
> + irq_map.rise[1] = BIT(4);
> + irq_map.rise[0] = BIT(0);
> + break;
> + case SOC_ARCH_EXYNOS5433:
> + case SOC_ARCH_EXYNOS7:
> + irq_map.fall[2] = BIT(23);
> + irq_map.fall[1] = BIT(17);
> + irq_map.fall[0] = BIT(16);
> + irq_map.rise[2] = BIT(7);
> + irq_map.rise[1] = BIT(1);
> + irq_map.rise[0] = BIT(0);
> + break;
> + default:
> + pr_warn("exynos-tmu: Unknown SoC type %d, using fallback IRQ mapping\n", soc);
> + break;
Maybe put irq_map inside exynos_tmu_data? exynos_map_dt_data has a
switch block that is quite similar, in that it also matches on the SoC
type. This way also there is no need to have a fallback.
Kind regards,
Mateusz Majewski
next prev parent reply other threads:[~2025-08-19 13:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-13 13:09 [PATCH v7 0/7] Exynos Thermal code improvement Anand Moon
2025-08-13 13:09 ` [PATCH v7 1/7] thermal/drivers/exynos: Refactor clk_sec initialization inside SOC-specific case Anand Moon
2025-08-13 13:09 ` [PATCH v7 2/7] thermal/drivers/exynos: Use devm_clk_get_enabled() helpers Anand Moon
2025-08-13 13:09 ` [PATCH v7 3/7] thermal/drivers/exynos: Remove redundant IS_ERR() checks for clk_sec clock Anand Moon
2025-08-13 13:09 ` [PATCH v7 4/7] thermal/drivers/exynos: Fixed the efuse min max value for exynos5422 Anand Moon
2025-08-13 13:09 ` [PATCH v7 5/7] thermal/drivers/exynos: Remove unused base_second mapping and references Anand Moon
2025-08-13 13:09 ` [PATCH v7 6/7] thermal/drivers/exynos: Handle temperature threshold IRQs with SoC-specific mapping Anand Moon
[not found] ` <CGME20250819131732eucas1p26bd491e9b6b747a4857905bfd50420a9@eucas1p2.samsung.com>
2025-08-19 13:17 ` Mateusz Majewski [this message]
[not found] ` <CGME20250819134804eucas1p1ed14f9680e66327a86af4e98319eed11@eucas1p1.samsung.com>
2025-08-19 13:47 ` Mateusz Majewski
2025-08-20 13:28 ` Anand Moon
2025-08-13 13:09 ` [PATCH v7 7/7] thermal/drivers/exynos: Refactor IRQ clear logic using SoC-specific config Anand Moon
[not found] ` <CGME20250819131814eucas1p2c57ccc084cf6736fed01a8a5c0b35fab@eucas1p2.samsung.com>
2025-08-19 13:18 ` Mateusz Majewski
2025-08-20 13:28 ` Anand Moon
2025-12-05 8:30 ` [PATCH v7 0/7] Exynos Thermal code improvement Anand Moon
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