From: K Prateek Nayak <kprateek.nayak@amd.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, <x86@kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>,
"Ahmed S. Darwish" <darwi@linutronix.de>,
K Prateek Nayak <kprateek.nayak@amd.com>
Subject: [PATCH 1/2] x86/cpu/cacheinfo: Convert get_cache_id() to use APIC ID and return Cache ID
Date: Thu, 21 Aug 2025 05:19:09 +0000 [thread overview]
Message-ID: <20250821051910.7351-2-kprateek.nayak@amd.com> (raw)
In-Reply-To: <20250821051910.7351-1-kprateek.nayak@amd.com>
Avoid reading the cpu_data() everytime get_cache_id() is called and
instead pass the APIC ID necessary to return the _cpuid4_info.id from
get_cache_id().
get_cache_id() will be used in the subsequent commit to assign llc_id
and not just the _cpuid4_info.id.
No functional changes intended.
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
arch/x86/kernel/cpu/cacheinfo.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index adfa7e8bb865..e7b10a612c6f 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -603,15 +603,15 @@ int init_cache_level(unsigned int cpu)
* ECX as cache index. Then right shift apicid by the number's order to get
* cache id for this cache node.
*/
-static void get_cache_id(int cpu, struct _cpuid4_info *id4)
+static unsigned int get_cache_id(u32 apicid, struct _cpuid4_info *id4)
{
- struct cpuinfo_x86 *c = &cpu_data(cpu);
unsigned long num_threads_sharing;
int index_msb;
num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
index_msb = get_count_order(num_threads_sharing);
- id4->id = c->topo.apicid >> index_msb;
+
+ return apicid >> index_msb;
}
int populate_cache_leaves(unsigned int cpu)
@@ -619,6 +619,7 @@ int populate_cache_leaves(unsigned int cpu)
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *ci = this_cpu_ci->info_list;
u8 cpu_vendor = boot_cpu_data.x86_vendor;
+ u32 apicid = cpu_data(cpu).topo.apicid;
struct amd_northbridge *nb = NULL;
struct _cpuid4_info id4 = {};
int idx, ret;
@@ -628,7 +629,7 @@ int populate_cache_leaves(unsigned int cpu)
if (ret)
return ret;
- get_cache_id(cpu, &id4);
+ id4.id = get_cache_id(apicid, &id4);
if (cpu_vendor == X86_VENDOR_AMD || cpu_vendor == X86_VENDOR_HYGON)
nb = amd_init_l3_cache(idx);
--
2.34.1
next prev parent reply other threads:[~2025-08-21 5:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-21 5:19 [PATCH 0/2] x86/cpu/cacheinfo: Simplify llc_id calculation on AMD platforms K Prateek Nayak
2025-08-21 5:19 ` K Prateek Nayak [this message]
2025-08-22 14:48 ` [tip: x86/cpu] x86/cpu/cacheinfo: Simplify cacheinfo_amd_init_llc_id() using _cpuid4_info tip-bot2 for K Prateek Nayak
2025-08-21 5:19 ` [PATCH 2/2] " K Prateek Nayak
2025-08-21 9:29 ` [PATCH 0/2] x86/cpu/cacheinfo: Simplify llc_id calculation on AMD platforms Borislav Petkov
2025-08-21 9:53 ` Ahmed S. Darwish
2025-08-21 10:22 ` Borislav Petkov
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