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[187.58.145.178]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4763fba7fcsm6039513a12.10.2025.08.21.21.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 21:41:02 -0700 (PDT) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, "Rafael V. Volkmer" Subject: [PATCH v5 1/6] pwm: tiehrpwm: use GENMASK()/FIELD_PREP() for register fields Date: Fri, 22 Aug 2025 01:40:24 -0300 Message-ID: <20250822044024.4015-1-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Make register field definitions use GENMASK() and FIELD_PREP() across AQCTL, AQCSFRC, and TBCTL. This clarifies bit layout, reduces hand-rolled shift logic, and aligns the driver with common kernel patterns. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 88 ++++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 41 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 0125e73b9..8509dd587 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -13,6 +13,7 @@ #include #include #include +#include /* EHRPWM registers and bits definitions */ @@ -21,15 +22,16 @@ #define TBPRD 0x0A #define TBCTL_PRDLD_MASK BIT(3) -#define TBCTL_PRDLD_SHDW 0 -#define TBCTL_PRDLD_IMDT BIT(3) -#define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ - BIT(8) | BIT(7)) -#define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) -#define TBCTL_CTRMODE_UP 0 -#define TBCTL_CTRMODE_DOWN BIT(0) -#define TBCTL_CTRMODE_UPDOWN BIT(1) -#define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) +#define TBCTL_PRDLD_SHDW FIELD_PREP(TBCTL_PRDLD_MASK, 0) +#define TBCTL_PRDLD_IMDT FIELD_PREP(TBCTL_PRDLD_MASK, 1) + +#define TBCTL_CLKDIV_MASK GENMASK(12, 7) + +#define TBCTL_CTRMODE_MASK GENMASK(1, 0) +#define TBCTL_CTRMODE_UP FIELD_PREP(TBCTL_CTRMODE_MASK, 0) +#define TBCTL_CTRMODE_DOWN FIELD_PREP(TBCTL_CTRMODE_MASK, 1) +#define TBCTL_CTRMODE_UPDOWN FIELD_PREP(TBCTL_CTRMODE_MASK, 2) +#define TBCTL_CTRMODE_FREEZE FIELD_PREP(TBCTL_CTRMODE_MASK, 3) #define TBCTL_HSPCLKDIV_SHIFT 7 #define TBCTL_CLKDIV_SHIFT 10 @@ -48,22 +50,25 @@ #define AQSFRC 0x1A #define AQCSFRC 0x1C -#define AQCTL_CBU_MASK (BIT(9) | BIT(8)) -#define AQCTL_CBU_FRCLOW BIT(8) -#define AQCTL_CBU_FRCHIGH BIT(9) -#define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) -#define AQCTL_CAU_MASK (BIT(5) | BIT(4)) -#define AQCTL_CAU_FRCLOW BIT(4) -#define AQCTL_CAU_FRCHIGH BIT(5) -#define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) -#define AQCTL_PRD_MASK (BIT(3) | BIT(2)) -#define AQCTL_PRD_FRCLOW BIT(2) -#define AQCTL_PRD_FRCHIGH BIT(3) -#define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) -#define AQCTL_ZRO_MASK (BIT(1) | BIT(0)) -#define AQCTL_ZRO_FRCLOW BIT(0) -#define AQCTL_ZRO_FRCHIGH BIT(1) -#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) +#define AQCTL_CBU_MASK GENMASK(9, 8) +#define AQCTL_CBU_FRCLOW FIELD_PREP(AQCTL_CBU_MASK, 1) +#define AQCTL_CBU_FRCHIGH FIELD_PREP(AQCTL_CBU_MASK, 2) +#define AQCTL_CBU_FRCTOGGLE FIELD_PREP(AQCTL_CBU_MASK, 3) + +#define AQCTL_CAU_MASK GENMASK(5, 4) +#define AQCTL_CAU_FRCLOW FIELD_PREP(AQCTL_CAU_MASK, 1) +#define AQCTL_CAU_FRCHIGH FIELD_PREP(AQCTL_CAU_MASK, 2) +#define AQCTL_CAU_FRCTOGGLE FIELD_PREP(AQCTL_CAU_MASK, 3) + +#define AQCTL_PRD_MASK GENMASK(3, 2) +#define AQCTL_PRD_FRCLOW FIELD_PREP(AQCTL_PRD_MASK, 1) +#define AQCTL_PRD_FRCHIGH FIELD_PREP(AQCTL_PRD_MASK, 2) +#define AQCTL_PRD_FRCTOGGLE FIELD_PREP(AQCTL_PRD_MASK, 3) + +#define AQCTL_ZRO_MASK GENMASK(1, 0) +#define AQCTL_ZRO_FRCLOW FIELD_PREP(AQCTL_ZRO_MASK, 1) +#define AQCTL_ZRO_FRCHIGH FIELD_PREP(AQCTL_ZRO_MASK, 2) +#define AQCTL_ZRO_FRCTOGGLE FIELD_PREP(AQCTL_ZRO_MASK, 3) #define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \ AQCTL_ZRO_FRCHIGH) @@ -74,22 +79,23 @@ #define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \ AQCTL_ZRO_FRCLOW) -#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) -#define AQSFRC_RLDCSF_ZRO 0 -#define AQSFRC_RLDCSF_PRD BIT(6) -#define AQSFRC_RLDCSF_ZROPRD BIT(7) -#define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) - -#define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) -#define AQCSFRC_CSFB_FRCDIS 0 -#define AQCSFRC_CSFB_FRCLOW BIT(2) -#define AQCSFRC_CSFB_FRCHIGH BIT(3) -#define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) -#define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) -#define AQCSFRC_CSFA_FRCDIS 0 -#define AQCSFRC_CSFA_FRCLOW BIT(0) -#define AQCSFRC_CSFA_FRCHIGH BIT(1) -#define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) +#define AQSFRC_RLDCSF_MASK GENMASK(7, 6) +#define AQSFRC_RLDCSF_ZRO FIELD_PREP(AQSFRC_RLDCSF_MASK, 0) +#define AQSFRC_RLDCSF_PRD FIELD_PREP(AQSFRC_RLDCSF_MASK, 1) +#define AQSFRC_RLDCSF_ZROPRD FIELD_PREP(AQSFRC_RLDCSF_MASK, 2) +#define AQSFRC_RLDCSF_IMDT FIELD_PREP(AQSFRC_RLDCSF_MASK, 3) + +#define AQCSFRC_CSFB_MASK GENMASK(3, 2) +#define AQCSFRC_CSFB_FRCDIS FIELD_PREP(AQCSFRC_CSFB_MASK, 0) +#define AQCSFRC_CSFB_FRCLOW FIELD_PREP(AQCSFRC_CSFB_MASK, 1) +#define AQCSFRC_CSFB_FRCHIGH FIELD_PREP(AQCSFRC_CSFB_MASK, 2) +#define AQCSFRC_CSFB_DISSWFRC FIELD_PREP(AQCSFRC_CSFB_MASK, 3) + +#define AQCSFRC_CSFA_MASK GENMASK(1, 0) +#define AQCSFRC_CSFA_FRCDIS FIELD_PREP(AQCSFRC_CSFA_MASK, 0) +#define AQCSFRC_CSFA_FRCLOW FIELD_PREP(AQCSFRC_CSFA_MASK, 1) +#define AQCSFRC_CSFA_FRCHIGH FIELD_PREP(AQCSFRC_CSFA_MASK, 2) +#define AQCSFRC_CSFA_DISSWFRC FIELD_PREP(AQCSFRC_CSFA_MASK, 3) #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ -- 2.43.0