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[187.58.145.178]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245f0d86c05sm64305745ad.93.2025.08.21.21.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 21:48:55 -0700 (PDT) From: "Rafael V. Volkmer" To: rafael.v.volkmer@gmail.com Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, ukleinek@kernel.org Subject: [PATCH v5 4/6] pwm: tiehrpwm: implement .get_state Date: Fri, 22 Aug 2025 01:48:06 -0300 Message-ID: <20250822044806.4103-1-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250822044545.4080-1-rafael.v.volkmer@gmail.com> References: <20250822044545.4080-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Implement ehrpwm_get_state() to report enable, period, duty cycle and polarity. Read AQCSFRC and AQCTL(A/B) to determine whether a channel is software-forced (treated as disabled) and expose current timing and polarity through the pwm_state. This lets consumers query the current hardware state reliably. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 103 +++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index b2a55e59b..1dae3b8b5 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -461,9 +461,112 @@ static int ehrpwm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return err; } +static int ehrpwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + int ret = 0; + + struct ehrpwm_pwm_chip *pc = NULL; + + /* Registers */ + u16 aqcsfrc_reg, aqctl_reg, tbprd_reg, tbctl_reg; + + /* Bits */ + u8 csf_bits, clkdiv_bits, hspclkdiv_bits; + + /* Values */ + u64 period_ticks, duty_ticks, ps_div; + + /* Actions */ + u8 up_action, down_action; + + pc = to_ehrpwm_pwm_chip(chip); + + /* + * The 'hwpwm' field identifies which hardware output channel (e.g., + * 0 for channel A and 1 for channel B) of the eHRPWM module is in use. + */ + if (pwm->hwpwm == 0) { + aqcsfrc_reg = readw(pc->mmio_base + AQCSFRC); + csf_bits = FIELD_GET(AQCSFRC_CSFA_MASK, aqcsfrc_reg); + aqctl_reg = readw(pc->mmio_base + AQCTLA); + } else { + aqcsfrc_reg = readw(pc->mmio_base + AQCSFRC); + csf_bits = FIELD_GET(AQCSFRC_CSFB_MASK, aqcsfrc_reg); + aqctl_reg = readw(pc->mmio_base + AQCTLB); + } + + if (csf_bits || !aqctl_reg) { + state->enabled = false; + return 0; + } + + state->enabled = true; + + tbprd_reg = readw(pc->mmio_base + TBPRD); + period_ticks = (u64)tbprd_reg + 1u; + + tbctl_reg = readw(pc->mmio_base + TBCTL); + hspclkdiv_bits = FIELD_GET(TBCTL_HSPCLKDIV_MASK, tbctl_reg); + clkdiv_bits = FIELD_GET(TBCTL_CLKDIV_MASK, tbctl_reg); + + ps_div = (1 << clkdiv_bits) * (hspclkdiv_bits ? (hspclkdiv_bits * 2) : 1); + + /* + * period (in ns) = (period_ticks * preescaler * 1e9) / clk_rate + * Using DIV_ROUND_UP_ULL to avoid floating-point operations. + */ + state->period = DIV_ROUND_UP_ULL(period_ticks * ps_div * NSEC_PER_SEC, pc->clk_rate); + + if (pwm->hwpwm == 0) + duty_ticks = readw(pc->mmio_base + CMPA); + else + duty_ticks = readw(pc->mmio_base + CMPB); + + /* + * duty_cycle (in ns) = (duty_ticks * preescaler * 1e9) / clk_rate + * Using DIV_ROUND_UP_ULL to avoid floating-point operations. + */ + state->duty_cycle = DIV_ROUND_UP_ULL(duty_ticks * ps_div * NSEC_PER_SEC, pc->clk_rate); + + /* + * The 'hwpwm' field identifies which hardware output channel (e.g., + * 0 for channel A and 1 for channel B) of the eHRPWM module is in use. + */ + if (pwm->hwpwm == 0) { + aqctl_reg = readw(pc->mmio_base + AQCTLA); + up_action = FIELD_GET(AQCTL_CAU_MASK, aqctl_reg); + down_action = FIELD_GET(AQCTL_CAD_MASK, aqctl_reg); + } else { + aqctl_reg = readw(pc->mmio_base + AQCTLB); + up_action = FIELD_GET(AQCTL_CBU_MASK, aqctl_reg); + down_action = FIELD_GET(AQCTL_CBD_MASK, aqctl_reg); + } + + /* + * Evaluate the actions to determine the PWM polarity: + * - If an up-count event sets the output (AQCTL_FRCHIGH) and a down-count + * event clears it (AQ_CLEAR), then polarity is NORMAL. + * - If an up-count event clears the output (AQ_CLEAR) and a down-count + * event sets it (AQCTL_FRCLOW), then polarity is INVERSED. + */ + if (up_action == AQCTL_FRCHIGH && down_action == AQCTL_FRCLOW) { + state->polarity = PWM_POLARITY_NORMAL; + } else if (up_action == AQCTL_FRCLOW && down_action == AQCTL_FRCHIGH) { + state->polarity = PWM_POLARITY_INVERSED; + } else { + state->polarity = PWM_POLARITY_NORMAL; + dev_dbg(&chip->dev, "ehrpwm: unknown polarity bits (0x%x/0x%x), defaulting to NORMAL\n", + up_action, down_action); + } + + return ret; +} + static const struct pwm_ops ehrpwm_pwm_ops = { .free = ehrpwm_pwm_free, .apply = ehrpwm_pwm_apply, + .get_state = ehrpwm_get_state, }; static const struct of_device_id ehrpwm_of_match[] = { -- 2.43.0