From: kernel test robot <lkp@intel.com>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org,
Marc Zyngier <maz@kernel.org>
Subject: drivers/irqchip/irq-gic-v5-irs.c:571 gicv5_irs_init_bases() warn: inconsistent indenting
Date: Fri, 22 Aug 2025 20:51:05 +0800 [thread overview]
Message-ID: <202508222051.ebaxHZ4Z-lkp@intel.com> (raw)
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 3957a5720157264dcc41415fbec7c51c4000fc2d
commit: 53bb952a625fd3247647c7a28366ce990a579415 arm64: Kconfig: Enable GICv5
date: 6 weeks ago
config: arm64-randconfig-r071-20250822 (https://download.01.org/0day-ci/archive/20250822/202508222051.ebaxHZ4Z-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508222051.ebaxHZ4Z-lkp@intel.com/
smatch warnings:
drivers/irqchip/irq-gic-v5-irs.c:571 gicv5_irs_init_bases() warn: inconsistent indenting
drivers/irqchip/irq-gic-v5-its.c:267 gicv5_its_create_itt_two_level() warn: always true condition '(i >= 0) => (0-u32max >= 0)'
drivers/irqchip/irq-gic-v5-its.c:267 gicv5_its_create_itt_two_level() warn: always true condition '(i >= 0) => (0-u32max >= 0)'
vim +571 drivers/irqchip/irq-gic-v5-irs.c
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 542
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 543 static void __init gicv5_irs_init_bases(struct gicv5_irs_chip_data *irs_data,
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 544 void __iomem *irs_base,
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 545 struct fwnode_handle *handle)
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 546 {
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 547 struct device_node *np = to_of_node(handle);
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 548 u32 cr0, cr1;
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 549
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 550 irs_data->fwnode = handle;
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 551 irs_data->irs_base = irs_base;
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 552
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 553 if (of_property_read_bool(np, "dma-noncoherent")) {
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 554 /*
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 555 * A non-coherent IRS implies that some cache levels cannot be
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 556 * used coherently by the cores and GIC. Our only option is to mark
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 557 * memory attributes for the GIC as non-cacheable; by default,
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 558 * non-cacheable memory attributes imply outer-shareable
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 559 * shareability, the value written into IRS_CR1_SH is ignored.
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 560 */
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 561 cr1 = FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_NO_WRITE_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 562 FIELD_PREP(GICV5_IRS_CR1_VPED_RA, GICV5_NO_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 563 FIELD_PREP(GICV5_IRS_CR1_VMD_WA, GICV5_NO_WRITE_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 564 FIELD_PREP(GICV5_IRS_CR1_VMD_RA, GICV5_NO_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 565 FIELD_PREP(GICV5_IRS_CR1_VPET_RA, GICV5_NO_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 566 FIELD_PREP(GICV5_IRS_CR1_VMT_RA, GICV5_NO_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 567 FIELD_PREP(GICV5_IRS_CR1_IST_WA, GICV5_NO_WRITE_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 568 FIELD_PREP(GICV5_IRS_CR1_IST_RA, GICV5_NO_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 569 FIELD_PREP(GICV5_IRS_CR1_IC, GICV5_NON_CACHE) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 570 FIELD_PREP(GICV5_IRS_CR1_OC, GICV5_NON_CACHE);
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 @571 irs_data->flags |= IRS_FLAGS_NON_COHERENT;
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 572 } else {
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 573 cr1 = FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_WRITE_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 574 FIELD_PREP(GICV5_IRS_CR1_VPED_RA, GICV5_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 575 FIELD_PREP(GICV5_IRS_CR1_VMD_WA, GICV5_WRITE_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 576 FIELD_PREP(GICV5_IRS_CR1_VMD_RA, GICV5_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 577 FIELD_PREP(GICV5_IRS_CR1_VPET_RA, GICV5_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 578 FIELD_PREP(GICV5_IRS_CR1_VMT_RA, GICV5_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 579 FIELD_PREP(GICV5_IRS_CR1_IST_WA, GICV5_WRITE_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 580 FIELD_PREP(GICV5_IRS_CR1_IST_RA, GICV5_READ_ALLOC) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 581 FIELD_PREP(GICV5_IRS_CR1_IC, GICV5_WB_CACHE) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 582 FIELD_PREP(GICV5_IRS_CR1_OC, GICV5_WB_CACHE) |
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 583 FIELD_PREP(GICV5_IRS_CR1_SH, GICV5_INNER_SHARE);
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 584 }
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 585
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 586 irs_writel_relaxed(irs_data, cr1, GICV5_IRS_CR1);
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 587
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 588 cr0 = FIELD_PREP(GICV5_IRS_CR0_IRSEN, 0x1);
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 589 irs_writel_relaxed(irs_data, cr0, GICV5_IRS_CR0);
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 590 gicv5_irs_wait_for_idle(irs_data);
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 591 }
5cb1b6dab2def3 Lorenzo Pieralisi 2025-07-03 592
:::::: The code at line 571 was first introduced by commit
:::::: 5cb1b6dab2def316671ea2565291a86ad58b884c irqchip/gic-v5: Add GICv5 IRS/SPI support
:::::: TO: Lorenzo Pieralisi <lpieralisi@kernel.org>
:::::: CC: Marc Zyngier <maz@kernel.org>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
reply other threads:[~2025-08-22 12:55 UTC|newest]
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