Re: [PATCH v4 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC

[Laura Nao <laura.nao@collabora.com>]

On 8/15/25 05:23, Chen-Yu Tsai wrote:
> On Tue, Aug 5, 2025 at 10:55 PM Laura Nao <laura.nao@collabora.com> wrote:
>>
>> MT8196 uses set/clr/upd registers for mux gate enable/disable control,
>> along with a FENC bit to check the status. Add new set of mux gate
>> clock operations with support for set/clr/upd and FENC status logic.
>>
>> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> Signed-off-by: Laura Nao <laura.nao@collabora.com>
>> ---
>>  drivers/clk/mediatek/clk-mtk.h |  2 ++
>>  drivers/clk/mediatek/clk-mux.c | 48 ++++++++++++++++++++++++++++++++++
>>  drivers/clk/mediatek/clk-mux.h | 45 +++++++++++++++++++++++++++++++
>>  3 files changed, 95 insertions(+)
>>
>> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
>> index c17fe1c2d732..136a4bc6dbe6 100644
>> --- a/drivers/clk/mediatek/clk-mtk.h
>> +++ b/drivers/clk/mediatek/clk-mtk.h
>> @@ -20,6 +20,8 @@
>>
>>  #define MHZ (1000 * 1000)
>>
>> +#define MTK_WAIT_FENC_DONE_US  30
>> +
>
> Nit: I think it would be nicer if you define this locally in the mux type
> clk code, just to keep the two completely separate.
>

Ack, will move this to clk-mux.c.

>>  struct platform_device;
>>
>>  /*
>> diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
>> index 60990296450b..b1b8eeb0b501 100644
>> --- a/drivers/clk/mediatek/clk-mux.c
>> +++ b/drivers/clk/mediatek/clk-mux.c
>> @@ -15,6 +15,7 @@
>>  #include <linux/spinlock.h>
>>  #include <linux/slab.h>
>>
>> +#include "clk-mtk.h"
>>  #include "clk-mux.h"
>>
>>  struct mtk_clk_mux {
>> @@ -30,6 +31,33 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
>>         return container_of(hw, struct mtk_clk_mux, hw);
>>  }
>>
>> +static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw)
>> +{
>> +       struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
>> +       unsigned long flags;
>> +       u32 val;
>> +       int ret;
>> +
>> +       if (mux->lock)
>> +               spin_lock_irqsave(mux->lock, flags);
>> +       else
>> +               __acquire(mux->lock);
>> +
>> +       regmap_write(mux->regmap, mux->data->clr_ofs,
>> +                    BIT(mux->data->gate_shift));
>> +
>> +       ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,
>> +                                             val, val & BIT(mux->data->fenc_shift), 1,
>> +                                             MTK_WAIT_FENC_DONE_US);
>> +
>> +       if (mux->lock)
>> +               spin_unlock_irqrestore(mux->lock, flags);
>> +       else
>> +               __release(mux->lock);
>> +
>> +       return ret;
>> +}
>> +
>>  static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
>>  {
>>         struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
>> @@ -70,6 +98,16 @@ static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
>>                         BIT(mux->data->gate_shift));
>>  }
>>
>> +static int mtk_clk_mux_fenc_is_enabled(struct clk_hw *hw)
>> +{
>> +       struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
>> +       u32 val;
>> +
>> +       regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
>> +
>> +       return val & BIT(mux->data->fenc_shift);
>
> Nit: Do a double negate.
>

Ack.

>> +}
>> +
>>  static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
>>  {
>>         struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
>> @@ -168,6 +206,16 @@ const struct clk_ops mtk_mux_gate_clr_set_upd_ops  = {
>>  };
>>  EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
>>
>> +const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops = {
>> +       .enable = mtk_clk_mux_fenc_enable_setclr,
>> +       .disable = mtk_clk_mux_disable_setclr,
>> +       .is_enabled = mtk_clk_mux_fenc_is_enabled,
>> +       .get_parent = mtk_clk_mux_get_parent,
>> +       .set_parent = mtk_clk_mux_set_parent_setclr_lock,
>> +       .determine_rate = mtk_clk_mux_determine_rate,
>> +};
>> +EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops);
>> +
>>  static struct clk_hw *mtk_clk_register_mux(struct device *dev,
>>                                            const struct mtk_mux *mux,
>>                                            struct regmap *regmap,
>> diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
>> index 943ad1d7ce4b..c65cfb7f8fc3 100644
>> --- a/drivers/clk/mediatek/clk-mux.h
>> +++ b/drivers/clk/mediatek/clk-mux.h
>> @@ -28,11 +28,13 @@ struct mtk_mux {
>>         u32 set_ofs;
>>         u32 clr_ofs;
>>         u32 upd_ofs;
>> +       u32 fenc_sta_mon_ofs;
>>
>>         u8 mux_shift;
>>         u8 mux_width;
>>         u8 gate_shift;
>>         s8 upd_shift;
>> +       u8 fenc_shift;
>>
>>         const struct clk_ops *ops;
>>         signed char num_parents;
>> @@ -77,6 +79,7 @@ struct mtk_mux {
>>
>>  extern const struct clk_ops mtk_mux_clr_set_upd_ops;
>>  extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
>> +extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops;
>>
>>  #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,     \
>>                         _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
>> @@ -118,6 +121,48 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
>>                         0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,         \
>>                         mtk_mux_clr_set_upd_ops)
>>
>> +#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx,         \
>> +                       _num_parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,     \
>> +                       _shift, _width, _gate, _upd_ofs, _upd,                  \
>> +                       _fenc_sta_mon_ofs, _fenc, _flags) {                     \
>> +               .id = _id,                                                      \
>> +               .name = _name,                                                  \
>> +               .mux_ofs = _mux_ofs,                                            \
>> +               .set_ofs = _mux_set_ofs,                                        \
>> +               .clr_ofs = _mux_clr_ofs,                                        \
>> +               .upd_ofs = _upd_ofs,                                            \
>> +               .fenc_sta_mon_ofs = _fenc_sta_mon_ofs,                          \
>> +               .mux_shift = _shift,                                            \
>> +               .mux_width = _width,                                            \
>> +               .gate_shift = _gate,                                            \
>> +               .upd_shift = _upd,                                              \
>> +               .fenc_shift = _fenc,                                            \
>> +               .parent_names = _parents,                                       \
>> +               .parent_index = _paridx,                                        \
>> +               .num_parents = _num_parents,                                    \
>> +               .flags = _flags,                                                \
>> +               .ops = &mtk_mux_gate_fenc_clr_set_upd_ops,                      \
>> +       }
>> +
>> +#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents,                        \
>> +                       _mux_ofs, _mux_set_ofs, _mux_clr_ofs,           \
>> +                       _shift, _width, _gate, _upd_ofs, _upd,          \
>> +                       _fenc_sta_mon_ofs, _fenc)                       \
>> +               MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents,   \
>> +                       NULL, ARRAY_SIZE(_parents), _mux_ofs,           \
>> +                       _mux_set_ofs, _mux_clr_ofs, _shift,             \
>> +                       _width, _gate, _upd_ofs, _upd,                  \
>> +                       _fenc_sta_mon_ofs, _fenc, 0)
>> +
>> +#define MUX_GATE_FENC_CLR_SET_UPD_INDEXED(_id, _name, _parents,        _paridx,        \
>
>                                                                    ^^^^^^
> This looks like a tab when it should have been a space?
>

Definitely - thanks for the heads up, I'll fix it.

Best,

Laura

> ChenYu
>
>> +                       _mux_ofs, _mux_set_ofs, _mux_clr_ofs,                   \
>> +                       _shift, _width, _gate, _upd_ofs, _upd,                  \
>> +                       _fenc_sta_mon_ofs, _fenc)                               \
>> +               MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx,  \
>> +                       ARRAY_SIZE(_paridx), _mux_ofs, _mux_set_ofs,            \
>> +                       _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, _upd,    \
>> +                       _fenc_sta_mon_ofs, _fenc, 0)
>> +
>>  int mtk_clk_register_muxes(struct device *dev,
>>                            const struct mtk_mux *muxes,
>>                            int num, struct device_node *node,
>> --
>> 2.39.5
>>