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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001708F.mail.protection.outlook.com (10.167.17.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9073.11 via Frontend Transport; Tue, 26 Aug 2025 04:16:06 +0000 Received: from BLRKPRNAYAK.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 25 Aug 2025 23:15:49 -0500 From: K Prateek Nayak To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , Christophe Leroy , Heiko Carstens , "Vasily Gorbik" , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , , "H. Peter Anvin" , Peter Zijlstra , Juri Lelli , Vincent Guittot , , , CC: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , , Li Chen , Bibo Mao , Mete Durlu , Tobias Huschle , "Easwar Hariharan" , Guo Weikang , "Rafael J. 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The scheduler uses CONFIG_SCHED_MC to introduce the MC domain in the default topology (core) and to optimize the default CPU selection routine (sched-ext). Introduce CONFIG_SCHED_MC for powerpc and note that it should be preferably enabled given the current default behavior. This also ensures PowerPC is tested during future developments that come to depend on CONFIG_SCHED_MC. Signed-off-by: K Prateek Nayak --- arch/powerpc/Kconfig | 9 +++++++++ arch/powerpc/include/asm/smp.h | 2 ++ arch/powerpc/kernel/smp.c | 4 ++++ 3 files changed, 15 insertions(+) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 93402a1d9c9f..e954ab3f635f 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -971,6 +971,15 @@ config SCHED_SMT when dealing with POWER5 cpus at a cost of slightly increased overhead in some places. If unsure say N here. +config SCHED_MC + bool "Multi-Core Cache (MC) scheduler support" + depends on PPC64 && SMP + default y + help + MC scheduler support improves the CPU scheduler's decision making + when dealing with POWER systems that contain multiple Last Level + Cache instances on the same socket. If unsure say Y here. + config PPC_DENORMALISATION bool "PowerPC denormalisation exception handling" depends on PPC_BOOK3S_64 diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h index 86de4d0dd0aa..9a320d96e891 100644 --- a/arch/powerpc/include/asm/smp.h +++ b/arch/powerpc/include/asm/smp.h @@ -148,7 +148,9 @@ static inline const struct cpumask *cpu_smt_mask(int cpu) } #endif /* CONFIG_SCHED_SMT */ +#ifdef CONFIG_SCHED_MC extern const struct cpumask *cpu_coregroup_mask(int cpu); +#endif /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers. * diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index e623f2864dc4..7f79b853b221 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -1059,6 +1059,7 @@ static bool has_coregroup_support(void) return coregroup_enabled; } +#ifdef CONFIG_SCHED_MC const struct cpumask *cpu_coregroup_mask(int cpu) { if (has_coregroup_support()) @@ -1071,6 +1072,7 @@ static const struct cpumask *cpu_mc_mask(struct sched_domain_topology_level *tl, { return cpu_corgrp_mask(cpu); } +#endif static const struct cpumask *cpu_pkg_mask(struct sched_domain_topology_level *tl, int cpu) { @@ -1729,10 +1731,12 @@ static void __init build_sched_topology(void) SDTL_INIT(shared_cache_mask, powerpc_shared_cache_flags, CACHE); } +#ifdef CONFIG_SCHED_MC if (has_coregroup_support()) { powerpc_topology[i++] = SDTL_INIT(cpu_mc_mask, powerpc_shared_proc_flags, MC); } +#endif powerpc_topology[i++] = SDTL_INIT(cpu_pkg_mask, powerpc_shared_proc_flags, PKG); -- 2.34.1