From: Xu Lu <luxu.kernel@bytedance.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH 0/2] riscv: mm: Some optimizations for tlb flush
Date: Wed, 27 Aug 2025 21:14:42 +0800 [thread overview]
Message-ID: <20250827131444.23893-1-luxu.kernel@bytedance.com> (raw)
Some optimizations for tlb flush on RISC-V smp:
1. Apply Svinval in update_mmu_cache().
2. Clear bit of current cpu in mm_cpumask after
local_flush_tlb_all_asid().
Xu Lu (2):
riscv: mm: Apply svinval in update_mmu_cache()
riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid
arch/riscv/include/asm/pgtable.h | 16 +++++++-
arch/riscv/include/asm/tlbflush.h | 23 +++++++++++
arch/riscv/mm/tlbflush.c | 64 ++++++++++++-------------------
3 files changed, 63 insertions(+), 40 deletions(-)
--
2.20.1
next reply other threads:[~2025-08-27 13:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-27 13:14 Xu Lu [this message]
2025-08-27 13:14 ` [PATCH 1/2] riscv: mm: Apply svinval in update_mmu_cache() Xu Lu
2025-08-27 13:14 ` [PATCH 2/2] riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid Xu Lu
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