From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 035161E1DE9; Mon, 1 Sep 2025 03:13:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756696401; cv=none; b=AgnK84n750zihiB9IZfwV+jRnefeU+iZcfq1QrpazLTvYnrEWiPXivqi7WLZ50gO/khPtrPZSbkXMc9bTgePfiZjhxGbYu2ad+OhUzVuXdny0ebgQkOrhNAnX3//M2QchvOjviGZdBcaSS7v4KBOSTJrUngQjdV+MB9gg1o3QSg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756696401; c=relaxed/simple; bh=T59K54wZyifk5hpHI1jQ+D+M1MJhrzhEGzmMgFCT4PE=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=k9rHtTDnbKRpw1/GwtbscVX3ct7jWrDDTfzTIE1LaKZiw62tav97hhEZYiqagBuaGCANwgKrxmL84fJc6k8fXugNQcm89uMIu9vmvkb8QRiI7jzrZGTuKrApPb7W/WB4y3IGoVkJmvz5M/bVKmB0sZzyWuhV7rKaay2rvRq/KT8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Sep 2025 11:13:11 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Sep 2025 11:13:11 +0800 From: Ryan Chen To: ryan_chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , , , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , , , , Subject: [PATCH v5 0/5] Introduce ASPEED AST2700 BMC SoC Date: Mon, 1 Sep 2025 11:13:06 +0800 Message-ID: <20250901031311.1247805-1-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain This introduces initial support for the Aspeed AST2700 SoC and the AST2700 Evaluation Board (EVB) to the Linux kernel. The AST27XX is the 8th generation Baseboard Management Controller (BMC) SoC from Aspeed, featuring improved performance, enhanced security, and expanded I/O capabilities compared to previous generations. AST27XX SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/ Bindings Dependencies: - intc-ic: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml - scu/silicon-id: Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml - gpio: Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml - mdio: Documentation/devicetree/bindings/net/aspeed,ast2600-mdio.yaml v5: - modify ast27XX 7th generation description to 8th generation. - aspeed.yaml - modify missing blank line. - Kconfig.platforms - modify ast27XX 7th generation to 8th generation. v4: - make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ fix. - modify commit message remove itemlize. - remove modify aspeed,ast2700-intc.yaml patch. - aspeed.yaml - Add AST2700 board compatible. - aspeed-g7.dtsi - modify all size-cells from 1 to 2. - add serial aliases, gpio, mdio, uart0 ~ 14. - add firmware for optee, reserved memory for atf and optee. - modify cpu@0 to cpu0: cpu@0. - fix intc-ic for yaml dependency. - ast2700-evb.dts - update stdout-path = "serial12:115200n8"; v3: - https://lore.kernel.org/all/20241212155237.848336-1-kevin_chen@aspeedtech.com/ - Split clk and reset driver to other commits, which are in series of "Add support for AST2700 clk driver". - For BMC console by UART12, add uart12 using ASPEED INTC architecture. aspeed,ast2700-intc.yaml - Add minItems to 1 to fix the warning by "make dtbs_check W=1". - Add intc1 into example. Kconfig.platforms - Remove MACH_ASPEED_G7. Ryan Chen (5): dt-bindings: arm: aspeed: Add AST2700 board compatible arm64: Kconfig: Add Aspeed SoC family (ast27XX) Kconfig support arm64: dts: aspeed: Add initial AST2700 SoC device tree arm64: dts: aspeed: Add AST2700 Evaluation Board arm64: configs: Update defconfig for AST2700 platform support .../bindings/arm/aspeed/aspeed.yaml | 6 + arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/Makefile | 4 + arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 452 ++++++++++++++++++ arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 22 + arch/arm64/configs/defconfig | 1 + 7 files changed, 492 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/Makefile create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts -- 2.34.1