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[47.55.120.4]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8069d6b1ff7sm162410985a.69.2025.09.02.09.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 09:29:00 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1utTsR-00000001ZjP-3QE9; Tue, 02 Sep 2025 13:28:59 -0300 Date: Tue, 2 Sep 2025 13:28:59 -0300 From: Jason Gunthorpe To: Baolu Lu Cc: Guanghui Feng , dwmw2@infradead.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, alikernel-developer@linux.alibaba.com Subject: Re: [PATCH] iommu/vt-d: fix iommu pasid memory alloc & max pasid err Message-ID: <20250902162859.GE184112@ziepe.ca> References: <20250830130737.1930726-1-guanghuifeng@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Sep 01, 2025 at 03:28:29PM +0800, Baolu Lu wrote: > On 8/30/25 21:07, Guanghui Feng wrote: > > When intel_pasid_alloc_table allocates memory for Scalable Mode PASID > > directories, the specified memory page order is incorrect, and an > > additional PAGE_SHIFT is added. There is also an error in calculating > > the maximum number of supported PASID directories. In the revised > > implementation, 1 << (order + PASID_PDE_SHIFT - 3) represents the memory > > occupied by the Scalable Mode PASID directory, divided by 8 to represent > > the number of PASID directories, and then multiplied by the number of (1 > > << PASID_PDE_SHIFT) entries in each PASID directory. > > Do you see any specific issues if the changes described in this patch > are lacking? > > > > > Signed-off-by: Guanghui Feng > > --- > > drivers/iommu/intel/pasid.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c > > index 52f678975da7..9969913b600b 100644 > > --- a/drivers/iommu/intel/pasid.c > > +++ b/drivers/iommu/intel/pasid.c > > @@ -61,14 +61,14 @@ int intel_pasid_alloc_table(struct device *dev) > > size = max_pasid >> (PASID_PDE_SHIFT - 3); > > order = size ? get_order(size) : 0; > > dir = iommu_alloc_pages_node_sz(info->iommu->node, GFP_KERNEL, > > - 1 << (order + PAGE_SHIFT)); > > + 1 << order); > > This converts the order to the allocation size. Yeah, I don't understand this patch at all, iommu_alloc_pages_node_sz() takes bytes and get_order(size) returns order. bytes == 1 << (get_order(size) + PAGE_SHIFT) Is correct So why is this being changed? Jason