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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?cuMW3J0ZPWlAZUVw8/kLlSkG991Z7qgZ4V9PmBEbYnq4iqd7GZD2aJEYM9XY?= =?us-ascii?Q?iicJrwcqXXoH0h1kmTWJ2YW/ezuoqsGxQWPTzYAS26uO5cLGb9uf8eQZhPwp?= =?us-ascii?Q?tLgp2ius4g9RjkH07bGbHI7OJPC8TRmN7zFi2HVZHrH1r+f7rJbaO1Cy+Z2n?= =?us-ascii?Q?pgF3o9T0saAyYGoN8vfLly8tTq6v0UWTni85+5uRA3qWogQgkd58S+sF5w0h?= =?us-ascii?Q?5jGl9hJtLZDhXhmea47Iq7BwW50A2A8aLCDwEVsPL4g+To+O2KeAmLPn/yoM?= =?us-ascii?Q?mWGQDmruvHJAq1Yw3gOD84KdsiiR8X8nRIlmFMMRCFWnH1ryrfdcbM4GIAYD?= =?us-ascii?Q?7C/wykGiKfG2en6nmxZjul2ENatPBX/cf0BKqcMVkMSqnt6ryBU0g5gxE2pL?= =?us-ascii?Q?cDPTVtLQLWbfG7as9lq0Ucc/mSmpFlMeB+vwfJdxMFeynm+QwT+jpKJ8xWKV?= =?us-ascii?Q?BBNNtFlU0E97IyIliXu+Dg6bgsqRJxbfIedILjVSTROR2LcDlvVqD3QqdeVe?= =?us-ascii?Q?F99kiolM1wYT3/NcFmIvXBA10RhisO6leD4iHFnIinwLnTT45ls6u9P8yLSZ?= =?us-ascii?Q?N1+KhF+MUjV4H3LVsG+5DgKduG+lj/iW1j0Dq0SjnwrPm/rBhBDTZ0b9rFGf?= =?us-ascii?Q?cv+T3xQpgcTrczoHbRTxNuMjA4ZawqsBpq6QEWrbXeF6EmhVaWBNqbarBuad?= =?us-ascii?Q?ZjuqcytYkkmC1LXKvugBD0NDfy/EkKtg9c7BMPx8WoF97oO1CDvjbkb3JT1/?= =?us-ascii?Q?Vuaqa7W6OgPvq1vBRZH8i5016yQjE7NAdUwv21ZZxxYmYy+t7kRSmZJvXWgo?= =?us-ascii?Q?pHPx5L2/PNRakREs7ffvJKlDqJp2BL8WV95ujOzNjkG9KIRLnNzGfDqb9RAF?= =?us-ascii?Q?rAyXcOxc3DOjnRhpLpTNzcBXEtjlcf1PdhAekpmMDrOUq2md7rus0rw1aJcs?= =?us-ascii?Q?mPnIhudUyk47ddkN8axXNgYDIs3ML/D/bBIFKPnIPMWBqg0cN33umh0Rcmkm?= =?us-ascii?Q?u5VLCO96Rm0Ra0Y5OzKMg6sW+iL7TBUmx2CU0HdwqMm8JiLz8vVzQ7R6poqA?= =?us-ascii?Q?C4N+w7MRJqdQ80YkvvRh0DOWU/xznD5s6AecpiselHxaG6n6OPUGm/ngf9+K?= =?us-ascii?Q?UXprOMUb+pJDG4/J2C7PclYu4vedDBhweO07+9tDbRYHiEsJhN05Ld6W1sUJ?= =?us-ascii?Q?SL4tHiFcOWETXbhMbFuUtjrafYMe3HtYdDNYFlCXrbvwddZN4liihLEChubH?= =?us-ascii?Q?Yd8sSVe782iBrPzJtSTRZPMXncTXuEpEOuVjbUv7hsXHrA9vxGlw8JsG8kZ/?= =?us-ascii?Q?TqwN6u+9TOHLjnZzImrMLQzH9R6hI5frQ8jPiEcx4hqCjuJfMF6Q7pWEA0Gm?= =?us-ascii?Q?Q4/GJOCyVcF0qcrCr4AqWINQ6rG3Y/S70FpEbHdtCg/1r4rI5yT9wYDQjQQN?= =?us-ascii?Q?mCqp9n0/HGeYoDA3bcYyut6qZwfUERZqw3o5UYDtQ6qOmO0VXs23J/HNh07I?= =?us-ascii?Q?NHCj3aKwv8jPmYICQUoyfuMmEb1HNrpqJsJc7Db+pQ8RWKzaC3/ZecO0LqFd?= =?us-ascii?Q?a6NXFIcvqi92b3BplKnqwFBu4u1BnZLxTtPfTY4Q?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03bf86c0-81cf-4e30-4074-08ddeaf23c86 X-MS-Exchange-CrossTenant-AuthSource: CY5PR12MB6369.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2025 14:00:27.8452 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: evqca6rO1DZo4LPKMuPCY00/tgA8c5M32sa98kLFBKZ7qN1mzj8kJga0Ag8xhZGwQaAIoXOaPjXKe1lV/Y8AGg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4378 On Wed, Sep 03, 2025 at 12:03:17PM +0200, Borislav Petkov wrote: > On Mon, Aug 25, 2025 at 05:33:12PM +0000, Yazen Ghannam wrote: > > Scalable MCA systems have a per-CPU register that gives the APIC LVT > > offset for the thresholding and deferred error interrupts. > > > > Currently, this register is read once to set up the deferred error > > interrupt and then read again for each thresholding block. Furthermore, > > the APIC LVT registers are configured each time, but they only need to > > be configured once per-CPU. > > > > Move the APIC LVT setup to the early part of CPU init, so that the > > registers are set up once. Also, this ensures that the kernel is ready > > to service the interrupts before the individual error sources (each MCA > > bank) are enabled. > > > > Apply this change only to SMCA systems to avoid breaking any legacy > > behavior. The deferred error interrupt is technically advertised by the > > SUCCOR feature. However, this was first made available on SMCA systems. > > Therefore, only set up the deferred error interrupt on SMCA systems and > > simplify the code. > > > > Guidance from hardware designers is that the LVT offsets provided from > > the platform should be used. The kernel should not try to enforce > > specific values. However, the kernel should check that an LVT offset is > > not reused for multiple sources. > > > > Therefore, remove the extra checking and value enforcement from the MCE > > code. The "reuse/conflict" case is already handled in > > setup_APIC_eilvt(). > > > > Tested-by: Tony Luck > > Reviewed-by: Tony Luck > > Signed-off-by: Yazen Ghannam > > Some touchups ontop: > > diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c > index c05d9c6f07d1..5722806ccaa5 100644 > --- a/arch/x86/kernel/cpu/mce/amd.c > +++ b/arch/x86/kernel/cpu/mce/amd.c > @@ -54,8 +54,10 @@ static bool thresholding_irq_en; > struct mce_amd_cpu_data { > mce_banks_t thr_intr_banks; > mce_banks_t dfr_intr_banks; > - bool thr_intr_en; > - bool dfr_intr_en; > + > + u32 thr_intr_en: 1, > + dfr_intr_en: 1, > + __resv: 30; > }; Thanks, I'll include these. But any reason to use u32? Why not u8? Alignment or something? The u32 is double the two bools that it replaces. Thanks, Yazen