From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 548F82AD00; Fri, 5 Sep 2025 05:19:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757049550; cv=none; b=RZ6o7qX9Tx7lJC4uCB44+OFcBmo6qhrbIwREuf5WEnbx0Q8CutllV9Z8fZg3PvOwEMOBVm8TN/PXmZ0ymJUkevSOtEJLcP2f+6tXf36rjLr3Mkm9ds3ElataP1KHbeECbjCc0hfDX+nuO1ACnCu2rAH0w7+ihS3yA0W3GTz4HeE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757049550; c=relaxed/simple; bh=TdCfkp5EjbF/XS45xMilQ0SXJKSp57L0iQjS4iChav0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ra37wFc8r55XgoB3DvHyNgbtZ3KESFjcfxj7FT0eqw/L7/tc8huixCvNu9b1fDYSfQoGX4MAq7G8Ma+gJ6G0edHIuHM5x8bBCM2F6dmmPE16eT3VpYITM4L2kJNvOkokTLwuznRIZ2iatsqwrv8HoDu8zVoSDyaj7bVbP9O/cDo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=OyWGSN7f; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="OyWGSN7f" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5855J4Y93246096; Fri, 5 Sep 2025 00:19:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757049544; bh=mt85MC02LFQ7xn6r0Pgl82alynes79oEBg/yND7jvjc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OyWGSN7flyjvNm43c1o6AcMPdnq/esSE1xBjIhOoFLtXoW/OHkI4vhOuzrSf1pelL 4p0yJtfcBMBsrLk7lVEIFUTWrvqXnzbo3an+s3QNhIywSLBalykjzXy54RhXRM42lb gleHPHxIBd+gxRVaM5J0r/wJMtQ84FVKLIPLxdOg= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5855J32W1404484 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 00:19:03 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 00:19:03 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 00:19:03 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5855IoiU220581; Fri, 5 Sep 2025 00:18:59 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v3 01/33] arm64: dts: ti: k3-j7200: Enable R5F remote processors at board level Date: Fri, 5 Sep 2025 10:48:14 +0530 Message-ID: <20250905051846.1189612-2-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905051846.1189612-1-b-padhi@ti.com> References: <20250905051846.1189612-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Remote Processors defined in top-level J7200 SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v3: Changelog: 1. Carried A/B tag. 2. Updated $subject to include R5F remote processors. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-2-b-padhi@ti.com/ v2: Changelog: 1. None Link to v1: https://lore.kernel.org/all/20250814223839.3256046-2-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 9 +++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5ce5f0a3d6f5..628ff89dd72f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -1516,6 +1516,7 @@ main_r5fss0: r5fss@5c00000 { ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j7200-r5f"; @@ -1530,6 +1531,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -1545,6 +1547,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 56ab144fea07..692c4745040e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -612,6 +612,7 @@ mcu_r5fss0: r5fss@41000000 { ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j7200-r5f"; @@ -626,6 +627,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -641,6 +643,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 291ab9bb414d..90befcdc8d08 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -254,20 +254,27 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ @@ -287,12 +294,14 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; }; &main_i2c0 { -- 2.34.1