Re: [PATCH v2 4/4] crypto: ti: Add support for AES-CCM in DTHEv2 driver

[kernel test robot <lkp@intel.com>]

Hi Pratham,

kernel test robot noticed the following build errors:

[auto build test ERROR on herbert-cryptodev-2.6/master]
[also build test ERROR on next-20250909]
[cannot apply to herbert-crypto-2.6/master linus/master v6.17-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/T-Pratham/crypto-ti-Add-support-for-AES-XTS-in-DTHEv2-driver/20250908-221357
base:   https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
patch link:    https://lore.kernel.org/r/20250908140928.2801062-5-t-pratham%40ti.com
patch subject: [PATCH v2 4/4] crypto: ti: Add support for AES-CCM in DTHEv2 driver
config: xtensa-allyesconfig (https://download.01.org/0day-ci/archive/20250909/202509091806.ibkQZYuz-lkp@intel.com/config)
compiler: xtensa-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250909/202509091806.ibkQZYuz-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509091806.ibkQZYuz-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/crypto/ti/dthev2-aes.c: In function 'dthe_aes_set_ctrl_key':
>> drivers/crypto/ti/dthev2-aes.c:258:29: error: implicit declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration]
     258 |                 ctrl_val |= FIELD_PREP(DTHE_AES_CTRL_CCM_L_MASK,
         |                             ^~~~~~~~~~


vim +/FIELD_PREP +258 drivers/crypto/ti/dthev2-aes.c

   186	
   187	static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx *ctx,
   188					  struct dthe_aes_req_ctx *rctx,
   189					  u32 *iv_in)
   190	{
   191		struct dthe_data *dev_data = dthe_get_dev(ctx);
   192		void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE;
   193		u32 ctrl_val = 0;
   194	
   195		writel_relaxed(ctx->key[0], aes_base_reg + DTHE_P_AES_KEY1_0);
   196		writel_relaxed(ctx->key[1], aes_base_reg + DTHE_P_AES_KEY1_1);
   197		writel_relaxed(ctx->key[2], aes_base_reg + DTHE_P_AES_KEY1_2);
   198		writel_relaxed(ctx->key[3], aes_base_reg + DTHE_P_AES_KEY1_3);
   199	
   200		if (ctx->keylen > AES_KEYSIZE_128) {
   201			writel_relaxed(ctx->key[4], aes_base_reg + DTHE_P_AES_KEY1_4);
   202			writel_relaxed(ctx->key[5], aes_base_reg + DTHE_P_AES_KEY1_5);
   203		}
   204		if (ctx->keylen == AES_KEYSIZE_256) {
   205			writel_relaxed(ctx->key[6], aes_base_reg + DTHE_P_AES_KEY1_6);
   206			writel_relaxed(ctx->key[7], aes_base_reg + DTHE_P_AES_KEY1_7);
   207		}
   208	
   209		if (ctx->aes_mode == DTHE_AES_XTS) {
   210			size_t key2_offset = ctx->keylen / sizeof(u32);
   211	
   212			writel_relaxed(ctx->key[key2_offset + 0], aes_base_reg + DTHE_P_AES_KEY2_0);
   213			writel_relaxed(ctx->key[key2_offset + 1], aes_base_reg + DTHE_P_AES_KEY2_1);
   214			writel_relaxed(ctx->key[key2_offset + 2], aes_base_reg + DTHE_P_AES_KEY2_2);
   215			writel_relaxed(ctx->key[key2_offset + 3], aes_base_reg + DTHE_P_AES_KEY2_3);
   216	
   217			if (ctx->keylen > AES_KEYSIZE_128) {
   218				writel_relaxed(ctx->key[key2_offset + 4], aes_base_reg + DTHE_P_AES_KEY2_4);
   219				writel_relaxed(ctx->key[key2_offset + 5], aes_base_reg + DTHE_P_AES_KEY2_5);
   220			}
   221			if (ctx->keylen == AES_KEYSIZE_256) {
   222				writel_relaxed(ctx->key[key2_offset + 6], aes_base_reg + DTHE_P_AES_KEY2_6);
   223				writel_relaxed(ctx->key[key2_offset + 7], aes_base_reg + DTHE_P_AES_KEY2_7);
   224			}
   225		}
   226	
   227		if (rctx->enc)
   228			ctrl_val |= DTHE_AES_CTRL_DIR_ENC;
   229	
   230		if (ctx->keylen == AES_KEYSIZE_128)
   231			ctrl_val |= DTHE_AES_CTRL_KEYSIZE_16B;
   232		else if (ctx->keylen == AES_KEYSIZE_192)
   233			ctrl_val |= DTHE_AES_CTRL_KEYSIZE_24B;
   234		else
   235			ctrl_val |= DTHE_AES_CTRL_KEYSIZE_32B;
   236	
   237		// Write AES mode
   238		ctrl_val &= DTHE_AES_CTRL_MODE_CLEAR_MASK;
   239		switch (ctx->aes_mode) {
   240		case DTHE_AES_ECB:
   241			ctrl_val |= AES_CTRL_ECB_MASK;
   242			break;
   243		case DTHE_AES_CBC:
   244			ctrl_val |= AES_CTRL_CBC_MASK;
   245			break;
   246		case DTHE_AES_CTR:
   247			ctrl_val |= AES_CTRL_CTR_MASK;
   248			ctrl_val |= DTHE_AES_CTRL_CTR_WIDTH_128B;
   249			break;
   250		case DTHE_AES_XTS:
   251			ctrl_val |= AES_CTRL_XTS_MASK;
   252			break;
   253		case DTHE_AES_GCM:
   254			ctrl_val |= AES_CTRL_GCM_MASK;
   255			break;
   256		case DTHE_AES_CCM:
   257			ctrl_val |= AES_CTRL_CCM_MASK;
 > 258			ctrl_val |= FIELD_PREP(DTHE_AES_CTRL_CCM_L_MASK,
   259					       (iv_in[0] & DTHE_AES_CCM_L_FROM_IV_MASK));
   260			ctrl_val |= DTHE_AES_CTRL_CCM_M_MAXVAL;
   261			break;
   262		}
   263	
   264		if (iv_in) {
   265			ctrl_val |= DTHE_AES_CTRL_SAVE_CTX_SET;
   266			for (int i = 0; i < AES_IV_WORDS; ++i)
   267				writel_relaxed(iv_in[i],
   268					       aes_base_reg + DTHE_P_AES_IV_IN_0 + (DTHE_REG_SIZE * i));
   269		}
   270	
   271		writel_relaxed(ctrl_val, aes_base_reg + DTHE_P_AES_CTRL);
   272	}
   273	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki