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Wed, 10 Sep 2025 08:58:09 -0700 (PDT) Received: from mai.box.freepro.com ([2a05:6e02:1041:c10:9717:723a:79cf:4f4a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e75223ea3csm7490325f8f.49.2025.09.10.08.58.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 08:58:08 -0700 (PDT) From: Daniel Lezcano To: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org Cc: linux-iio@vger.kernel.org, s32@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 0/2] NXP SAR ADC IIO driver for s32g2/3 platforms Date: Wed, 10 Sep 2025 17:57:54 +0200 Message-ID: <20250910155759.75380-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The S32G2 and S32G3 platforms have a couple of successive approximation register (SAR) ADCs with eight channels and 12-bit resolution. These changes provide the driver support for these ADCs and the bindings describing them. The driver is derived from the BSP driver version. It has been partly rewritten to conform to upstream criteria. https://github.com/nxp-auto-linux/linux/blob/release/bsp44.0-6.6.85-rt/drivers/iio/adc/s32cc_adc.c After the V1 posting there were some discussions around the DMA code to be converted to use the IIO DMA API [1]. Unfortunately this one is not yet fully implemented and merged in the framework to support the cyclic DMA. The current DMA code in the driver has been used in production since several years and even if I agree it can be improved with a dedicated IIO DMA API in the future, IMO, it sounds reasonable to keep it as is until the IIO DMA API supporting the cyclic DMA is merged. I'll be glad to convert the driver code if such an API exists and allows to remove code inside the driver. [1] https://lore.kernel.org/all/c30bb4b6328d15a9c213c0fa64b909035dc7bf40.camel@gmail.com/ Changelog: * V2: - Massaged the cover letter changelog to explain the DMA ** Andriy Shevchenko ** - Added missing headers and use proper header for of.h - Changed macro offset zero to be consistent - Remove macros REG_ADC_MCR_NRSMPL_* as they are unused - Changed delays macro under the form 100000 => 100 * USEC_PER_MSEC - Replaced PAGE_SIZE by a NXP_PAGE_SIZE = SZ_4K macro - Replaced read_poll_timeout() by readl_poll_timeout() - Changed error pattern "error first" - Replaced variable type 'int' to 'unsigned int' - Fixed bug right instead of left shift, use BIT(channel) - Returned directly from switch-case - Used guard(spinlock_irqsave)() - One liner function call - Remove redundant {} - Write default values litterals instead of temporary variables - Changed variable name vref -> vref_mV - Removed unneeded error message - Used dev_err_probe() consistently - Removed successful driver probe message - Removed redundant blank line ** Nuno Sa ** - Replaced of_device_get_match_data() by device_get_match_data() - Removed iio_device_unregister() because devm_iio_device_register() is used - Removed "/* sentinel */" comment - Removed CONFIG_PM_SLEEP defiries ** Krzysztof Kozlowski / David Lechner ** - Removed clock-names in DT bindings - Fixed minItems by maxItems * V1: - Initial post Daniel Lezcano (2): dt-bindings: iio: adc: Add the NXP SAR ADC for s32g2/3 platforms iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms .../bindings/iio/adc/nxp,s32g2-sar-adc.yaml | 63 + drivers/iio/adc/Kconfig | 13 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/nxp-sar-adc.c | 1026 +++++++++++++++++ 4 files changed, 1103 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml create mode 100644 drivers/iio/adc/nxp-sar-adc.c -- 2.43.0