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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?M0QOgKlFVAE7GUZ5rvVans1e4y1Cx+PTurXUYImnaIXnKff3jPJ4YXXmD+PK?= =?us-ascii?Q?F1+nloaY8CLfqow+OZW6DRKFeUGZ8AwyIMre4NW6fYZOisl5qKL8WHlv42l3?= =?us-ascii?Q?NetGcRlnMgDpBjiiODJhMQn4RRcJXC8IP9zPAu2zD4FCNUte7m+1m/r7jBZz?= =?us-ascii?Q?fUzh0PHaN26VI20bgbtJ0VHWmqS5cDHiLjM+xYUg+0F/Bc5v4aq1FHPOv1A9?= =?us-ascii?Q?yGF3tPCiq9RZp0aiISvxtiJO7pn0nlPlGz7/SAKuCM41i5imXeeqUuwNFlVl?= =?us-ascii?Q?YD+SyU1tJpBxLkryS0YLSX+hYGB2W40e4Fln5zQGURU1X0apEVwe7nzFPAXF?= =?us-ascii?Q?mCvFotCwBCvWyS4wyNBOYH2VGgt5DJit73941Xt4L5oEg3nmTa+Y8peZGqQH?= =?us-ascii?Q?iSGAQ09JhSMRQ/4NiQJlXkdHDYTTOUP3sv3npRF5Qh65lEN+sx5XYY+EEEoO?= =?us-ascii?Q?qHXuDP2bTtDUDxCu8Ihslebs77QkSZejWy66dN/qlsTJvET8HQHWLISowpgn?= =?us-ascii?Q?MzOrmCEDBX9mVCU5zn8nWU+VzgPMwYUL+lcpnLwhzWv4JpjpfipXqfNYwHt5?= =?us-ascii?Q?V128DxhrEWdLe8Mxtu4+wdrjWD2eO3+G6AJrfHzOBTumSHgNF+D5KuDzZcZM?= =?us-ascii?Q?6U6AnaYLQF9dIN3ZsQIYcBESq2R/f+oJVTzVUF3tetiXcgwknKMnFsDNxu75?= =?us-ascii?Q?hYK+vmSU8YetPuOegKyKKp//7bj/drA3o5htDPzTTFUwNNopz/HmmOU09kJd?= =?us-ascii?Q?P7mJM6KMPGM8LAr6itCwA3mOc7at/Iusitjjq8uydhSn/Y0StfbdeZZEVodt?= =?us-ascii?Q?aZT2BSz8sBGUZPGrHMSrdwxUfqKqZBgda7OynaZFntY4N1xj1oxSl02WsTeV?= =?us-ascii?Q?OBSWjv3iVx5vtZEi7ATA2eTNngjQzD0t3/pwkzXViVTfiSjEiPD9ixpBwJNw?= =?us-ascii?Q?TN5uN8gX/yRJgVZbfc4GZ6itdrkVGYGxJvQmrITZ+Eh9dYqUfWCPudC2qqIR?= =?us-ascii?Q?x2PbiKvAFpzJ8+vwmxNeKNQ5N9F7T4/OOR2XyNNX2E6wqJbJeUrIclC36opR?= =?us-ascii?Q?VWzzKvaRfiwBr0Z7+OBiymnvWfxo1wW/bcZxmUcT+nMpmgK0/G2Q9ZyzOGsh?= =?us-ascii?Q?+SQMVIKq4YdowJCnN9bb3gzL0Sj/ZQI1elA1+88Wb5Mwgj0T/p84yNzXKHWC?= =?us-ascii?Q?2JYJaUcPjOnbJrDvct8DUEoj4oG5v/xmlxfDc2sUBI91IDuhElFmKmaCqmSW?= =?us-ascii?Q?+Q8dAkeKNOW0hc1ZxgxZu7k1n48U+qgdzgkasGvJsbOkWwEkimLGsLpFI5jV?= =?us-ascii?Q?SOOG4bi7kpa32f8EtVdZlRTc9pBbCJSn8GbF8zmYbZJPhkRAE16JxFPplfmk?= =?us-ascii?Q?c10+AJSN4BbQuMcnjCeQVzwlCVt1cgfJ8uHlpx3B1cVlrU65kGVgfgiukDJm?= =?us-ascii?Q?Lud2Jc6WPwOg9cSBelYOt3vIfalMYa8attNyBpb50igEaqHpjjwP3x2HKYwJ?= =?us-ascii?Q?k1OXaUdHoJ6U1q7UF1iCzXIYZwj4Y3D/NCQip82Ek5ojIvmQilEKYGxl2jUC?= =?us-ascii?Q?4jYKSmCD+HTi7UcrASZFTgOYZUT9+hMcq6jr9xGz?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86079f10-a86b-41ef-d411-08ddf14b544c X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 15:53:21.5467 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dRODD4LcwJpjhFrxfMEzH0H0M20U/zGpT0CXLG5mLCki41bMqRRvWsERVfiRBG2VzylAwxWoobTERY4Vw0xQnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6272 On Thu, Sep 11, 2025 at 01:22:10PM +0300, Nikolay Borisov wrote: > > > On 9/8/25 18:40, Yazen Ghannam wrote: > > Scalable MCA systems have a per-CPU register that gives the APIC LVT > > offset for the thresholding and deferred error interrupts. > > > > Currently, this register is read once to set up the deferred error > > interrupt and then read again for each thresholding block. Furthermore, > > the APIC LVT registers are configured each time, but they only need to > > be configured once per-CPU. > > > > Move the APIC LVT setup to the early part of CPU init, so that the > > registers are set up once. Also, this ensures that the kernel is ready > > to service the interrupts before the individual error sources (each MCA > > bank) are enabled. > > > > Apply this change only to SMCA systems to avoid breaking any legacy > > behavior. The deferred error interrupt is technically advertised by the > > SUCCOR feature. However, this was first made available on SMCA systems. > > Therefore, only set up the deferred error interrupt on SMCA systems and > > simplify the code. > > > > Guidance from hardware designers is that the LVT offsets provided from > > the platform should be used. The kernel should not try to enforce > > specific values. However, the kernel should check that an LVT offset is > > not reused for multiple sources. > > > > Therefore, remove the extra checking and value enforcement from the MCE > > code. The "reuse/conflict" case is already handled in > > setup_APIC_eilvt(). > > > > Tested-by: Tony Luck > > Reviewed-by: Tony Luck > > Signed-off-by: Yazen Ghannam > > --- > > > > Notes: > > Link: > > https://lore.kernel.org/r/20250825-wip-mca-updates-v5-15-865768a2eef8@amd.com > > v5->v6: > > * Applied "bools to flags" and other fixups from Boris. > > v4->v5: > > * Added back to set. > > * Updated commit message with more details. > > v3->v4: > > * Dropped from set. > > v2->v3: > > * Add tags from Tony. > > v1->v2: > > * Use new per-CPU struct. > > * Don't set up interrupt vectors. > > > > arch/x86/kernel/cpu/mce/amd.c | 121 ++++++++++++++++++------------------------ > > 1 file changed, 53 insertions(+), 68 deletions(-) > > > > diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c > > index 1b1b83b3aef9..a6f5c9339d7c 100644 > > --- a/arch/x86/kernel/cpu/mce/amd.c > > +++ b/arch/x86/kernel/cpu/mce/amd.c > > @@ -43,9 +43,6 @@ > > /* Deferred error settings */ > > #define MSR_CU_DEF_ERR 0xC0000410 > > nit: While touching this code why not finally rename this in line with the > APM, section 9.3.1.4: MCA_INTR_CFG > > Perhaps as a separate patch. I see that you did send a patch containing this > rename: > https://lore.kernel.org/all/20231118193248.1296798-13-yazen.ghannam@amd.com/ > But I guess it didn't land. Yep, thanks for noticing. :) IIRC, I tried to reduce this set down to (mostly) functional changes. I think that there is still more worthwhile refactoring to do. Thanks, Yazen