From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D66CD35A28C; Thu, 11 Sep 2025 15:57:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757606255; cv=none; b=TQ7DuhGMucVY++fkDmec/bKH9wPuZA9jnLgsRgYGUvUOuyFezALXE1kEmRPYMu+Fzia4nuAY/fdzHLuHulfHLMuxFBoMYCssbFD8lwm5i2KbZuT2gRLaH1yNBhIpXxpB10knHb4IVC2/FxKxVikU0leLU0uGYhg21t9tElgABBA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757606255; c=relaxed/simple; bh=b1HZDQqQsYr58FY+10TUUiHUY+LFzqNmIFdIpqRJYYc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b6Bq/dfMJycgEtcOn2ZeVxKCLD4ZVUhZarBQ/zNT0L0US+Fy8I5pIyfVfhYgH6H2zdxckcjgSf4F26bwb4HPRg3wd6+r5hUedJfbd9UTyt6FPOiJcF4Jz8LhlNAD232EQNg7hWsxdbJOlTrbpQi6/kImqO7o0wCZpNnNyAx+C1k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ZI4sMszk; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ZI4sMszk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1757606249; bh=b1HZDQqQsYr58FY+10TUUiHUY+LFzqNmIFdIpqRJYYc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZI4sMszkrwaBn1LN54d6++i9mLnDvATVaOA/bFz3+q4DhlpXWT1SfYe3i8yycDWcF DJprBk24SkM3bk/zG2t9tOGxw0F4rSa+cictkNeFzh4SccsUbp8qzVxT2DZb1rZTvb cWyN9nXha/SoKhj0hQzAJoK6WiMdlW77oKR+i/Cq/pmKUeeAKjGYuY7p31NuJRZ1v2 SKjWLc4fD4d16N1cwOGJ7GD436YiYmVdrs3A0PYFog9A/OdphQ49IzpJu8K9F8yXKV tdqDfPcrpXrWbtnhv2Pxy66Wb9qv6GJlRpIql/oG8iTctsuRfq3Knx2VOd5jHhQE3T kE4wC3rrM/g0g== Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:36e5:357f:56a7:54dd]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3873A17E1287; Thu, 11 Sep 2025 17:57:29 +0200 (CEST) From: Benjamin Gaignard To: joro@8bytes.org, robin.murphy@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, nicolas.dufresne@collabora.com, jgg@ziepe.ca, p.zabel@pengutronix.de, mchehab@kernel.org Cc: iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-media@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v9 5/7] media: verisilicon: AV1: Restore IOMMU context before decoding a frame Date: Thu, 11 Sep 2025 17:57:15 +0200 Message-ID: <20250911155720.180465-6-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250911155720.180465-1-benjamin.gaignard@collabora.com> References: <20250911155720.180465-1-benjamin.gaignard@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit AV1 is a stateless decoder which means multiple AV1 bitstreams could be decoded at the same time using the same hardware block. Before decoding a frame it is needed to restore the iommu tables to avoid mixing decode contexts. Signed-off-by: Benjamin Gaignard --- .../verisilicon/rockchip_vpu981_hw_av1_dec.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c index e4703bb6be7c..d9e68e0ded68 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c @@ -5,6 +5,9 @@ * Author: Benjamin Gaignard */ +#include +#include + #include #include "hantro.h" #include "hantro_v4l2.h" @@ -2095,12 +2098,24 @@ rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx) hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr); } +static void rockchip_vpu981_av1_restore_iommu(struct hantro_ctx *ctx) +{ + struct iommu_domain *domain; + + /* Before decoding any frame iommu context need to be restored */ + domain = iommu_get_domain_for_dev(ctx->dev->v4l2_dev.dev); + if (domain) + vsi_iommu_restore_ctx(domain); +} + int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; struct vb2_v4l2_buffer *vb2_src; int ret; + rockchip_vpu981_av1_restore_iommu(ctx); + hantro_start_prepare_run(ctx); ret = rockchip_vpu981_av1_dec_prepare_run(ctx); -- 2.43.0