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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2025 10:37:32.0889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3574028f-5ef7-4043-c4f4-08ddf443e074 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7737 - CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the CPUID and MCAMSR protocol to return error, "-EOPNOTSUPP", for revision 0x21. - Next set of patches will add support for CPUID and MCAMSR for Turin and later platforms. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta --- Changes since v1: - New patch drivers/misc/amd-sbi/rmi-core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 3dec2fc00124..bf534ba757db 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -122,8 +122,8 @@ static int rmi_cpuid_read(struct sbrmi_data *data, if (ret < 0) goto exit_unlock; } - /* CPUID protocol for REV 0x10 is not supported*/ - if (data->rev == 0x10) { + /* CPUID protocol for REV 0x20 is only supported*/ + if (data->rev != 0x20) { ret = -EOPNOTSUPP; goto exit_unlock; } @@ -203,8 +203,8 @@ static int rmi_mca_msr_read(struct sbrmi_data *data, if (ret < 0) goto exit_unlock; } - /* MCA MSR protocol for REV 0x10 is not supported*/ - if (data->rev == 0x10) { + /* MCA MSR protocol for REV 0x20 is supported*/ + if (data->rev != 0x20) { ret = -EOPNOTSUPP; goto exit_unlock; } -- 2.25.1