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Tue, 16 Sep 2025 06:22:56 -0700 (PDT) Received: from [127.0.0.1] ([101.76.241.248]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7761562f25dsm13277310b3a.74.2025.09.16.06.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 06:22:56 -0700 (PDT) From: Zixian Zeng Subject: [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Date: Tue, 16 Sep 2025 21:22:49 +0800 Message-Id: <20250916-sfg-spidts-v2-0-b5d9024fe1c8@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKlkyWgC/23Myw6DIBCF4Vcxsy4NULXiqu/RuFAZcJJ6CWNIG 8O7l7ru8j/J+Q5gDIQMbXFAwEhM65JDXwoYp37xKMjmBi11JRt1E+y84I3szgKxqmVZmto4hHz YAjp6n9izyz0R72v4nHZUv/UvE5WQwpjhjnrAxljz8HNPr+u4ztCllL5rQK5+pAAAAA== X-Change-ID: 20250813-sfg-spidts-ee56044969fe To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Han Gao , Longbin Li , Zixian Zeng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758028972; l=1435; i=sycamoremoon376@gmail.com; s=20250113; h=from:subject:message-id; bh=CGgTSIYt63qsmZdwIds4EcFmwLudv2lGpTjjwlt+HoE=; b=frGV+4xLcAYmFm8cXKHpsQaD0uBvclAaMVxAAhak1hE/IpCvgEap926nsl9BMP/TlwV0EZZ+P mFr1wUbMukKDMfYQpgs48Il27cqhMfYZvRtaGw2q/TNe6z0g4TVVak7 X-Developer-Key: i=sycamoremoon376@gmail.com; a=ed25519; pk=OYfH6Z2Nx3aU1r0UZdvhskmddV6KC6V1nyFjsQQt4J8= [PATCH 1/4] and [PATCH 2/4] are copied from patch set [1] [PATCH v4 4/4] with content changes: According to SG2042 Pioneer and SG2042_EVB_V1/V2 schematics, SPI-NOR Flash cannot support QSPI due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1. Link: https://lore.kernel.org/linux-riscv/20250720-sfg-spifmc-v4-0-033188ad801e@gmail.com/ [1] Signed-off-by: Zixian Zeng --- Changes in v2: - Change value of spi-(tx|rx)-bus-width properties to 1 of all boards. - Decrease spi-max-frequency to 50MHz. - Link to v1: https://lore.kernel.org/r/20250813-sfg-spidts-v1-0-99b7e2be89d9@gmail.com --- Zixian Zeng (4): riscv: dts: sophgo: Add SPI NOR node for SG2042 riscv: dts: sophgo: Enable SPI NOR node for PioneerBox riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 24 ++++++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 +++++++++++ .../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 24 ++++++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 24 ++++++++++++++++++++++ 4 files changed, 84 insertions(+) --- base-commit: 8a4fdd09c96f6713e6cb47d36e9f9dd6f6694215 change-id: 20250813-sfg-spidts-ee56044969fe Best regards, -- Zixian Zeng