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[47.55.120.4]) by smtp.gmail.com with ESMTPSA id af79cd13be357-83627d7dd01sm169419185a.27.2025.09.18.07.11.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Sep 2025 07:11:02 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1uzFLi-00000008vyr-1Vsu; Thu, 18 Sep 2025 11:11:02 -0300 Date: Thu, 18 Sep 2025 11:11:02 -0300 From: Jason Gunthorpe To: manivannan.sadhasivam@oss.qualcomm.com Cc: Bjorn Helgaas , Joerg Roedel , Will Deacon , Robin Murphy , Greg Kroah-Hartman , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Joerg Roedel , iommu@lists.linux.dev, Anders Roxell , Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , stable@vger.kernel.org Subject: Re: [PATCH 0/2] PCI: Fix ACS enablement for Root Ports in DT platforms Message-ID: <20250918141102.GO1326709@ziepe.ca> References: <20250910-pci-acs-v1-0-fe9adb65ad7d@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250910-pci-acs-v1-0-fe9adb65ad7d@oss.qualcomm.com> On Wed, Sep 10, 2025 at 11:09:19PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > This issue was already found and addressed with a quirk for a different device > from Microsemi with 'commit, aa667c6408d2 ("PCI: Workaround IDT switch ACS > Source Validation erratum")'. Apparently, this issue seems to be documented in > the erratum #36 of IDT 89H32H8G3-YC, which is not publicly available. This is a pretty broken device! I'm not sure this fix is good enough though. For instance if you reset a downstream device it should loose its RID and then the config cycles waiting for reset to complete will trigger SV and reset will fail? Maybe a better answer is to say these switches don't support SV and prevent the kernel from enabling it in the first place? Jason