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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?4f5Gre9eeonYXtQvSdrRvOckYGT/9MH+yG+esAPEF5W1MsHE36N8F/+8V4FH?= =?us-ascii?Q?+COIfgPfeXrIBi1d164KumxqRrgu7YKasGBBa5a957YVKbSbwcLzlJA+YK+W?= =?us-ascii?Q?7obF16KpNCNnsWggJw/8IuatPJbE2ZA0OS4glFErmW6uZLfMqYnce8YsJikb?= =?us-ascii?Q?K0dhHxNIBBii0Gwcllr8rYPx8d+XnaOMSTtVRAqibr9hLX+uph5GdRFBxxuf?= =?us-ascii?Q?FtBPKbp34vILyLnB6wcth6KW+spzaEezR6G4G4GvaR3f1g3VKKZxPL5fFkT4?= =?us-ascii?Q?t6tqZLGL3Mo679zEMeNfrC0LTXO+zWKBuzpoLyPmtt0oy8BLKCK5zkOCSxr4?= =?us-ascii?Q?VxP4vUCIgW4vRCJqcGzZsXSfcHqiu8Rpld3WAQPZm/yn676KK4JvrYrS6Tjv?= =?us-ascii?Q?1YSMG0VgEF2gH6uPGuNwQe+7XclrpHQX0mdLBQjoeO8T+RVfWaStMY0jL8/W?= =?us-ascii?Q?fbYqzx+k3MWvpTOe43dt5nPXB+jgP9K5D+PQKivYZUIxoNvOGrks4GDESzVX?= =?us-ascii?Q?QntgC2tK5FgYoxnuDOda1IfxEUVroARjuznULbfPGxwQqqIhmqhHVusiOjer?= =?us-ascii?Q?zZXmlsL2gkE7YX3SAjojYw/PzJUGqWEjnsxk6H8N1vSrU/0PhFl9OFTNtg5Z?= =?us-ascii?Q?SYQoiZYReXnuTeRV2S7eITB7bjFAvBuWtye/YjRhQ0j/Q17PYSt5add5P3nZ?= =?us-ascii?Q?rtUqyZsNAFZ6WfYLy1glIdOSGFv+FpqxhD0l2nE8jy4CZ5GHN6olui2T7Rx9?= =?us-ascii?Q?nSZW0wQbO5ag+C7yKU2oUQKfhAZyfUkmmQ1sFeglF1YSzlTvvBc/3ErS0VRr?= =?us-ascii?Q?4BJ6HvXIlTR4rIWuJcKguTDZzZQETAFtYmEB+iwU/Ud/gtV9ucSTuwujMrFX?= =?us-ascii?Q?ui97VksHn9YzToi5Mrt+tPPyz/snUY1/eeXq9BPWik9tFShEGLN0nyeUaSb1?= =?us-ascii?Q?8HnHBGJon3yfoaZ+6Gi0pTLv4uWSh8jL24m55zACGMl5UFzydgysFd5T0WbJ?= =?us-ascii?Q?fCjcALsI9/x+k3dRewS4vE3e8pthI/vQo4NV+hQriPXFCcBRCCBTQM+DwnZL?= =?us-ascii?Q?75Lj6IAkKdl6Pvr3nre6ykEHIjwcKdFMIErPDkJN9HZARPHhY3A6xMX0Vudd?= =?us-ascii?Q?eZvV3NFyoL14QfL8d7arZeB14gWyWYjz/Odk2DRP1iYjL0ZqQBfWWw5pPT3+?= =?us-ascii?Q?esGj6ZRzmtZzIOvB2gAd9PYSoFNu5OEiF1xI1PunaNRVFabalAgt1vamn6zd?= =?us-ascii?Q?fisOZ1UfCZBCF/6E5sXjtcQR4Id7JK5olAl6lJ1GH3AVblqcKZUdvpN/WyLc?= =?us-ascii?Q?LAWU54Ybxwa7ArEwsDWHaQPHVsF464CdncUO0n4dOka1/egBIqbpJx1t+Tha?= =?us-ascii?Q?aIf3zmmxB0I3scJDaxCcs22QU6VBqI4vk3Gpb84+zCB9rRejFZl8/Tb0OiCV?= =?us-ascii?Q?QSUyFas9oncmFVfPei4hYo7fV36M0SE0CCGGcxqq1tv8OucKntqYyRtnKrK4?= =?us-ascii?Q?XsJ1clHPLR4v7gVctXgH7WaKV+uBYU/0xCWG9BYQ7C3HhcZ40QnphzS7urEE?= =?us-ascii?Q?Dt3tpXf7B7qtqY0077lmV0AQ2c5Jq9ukv985BcND?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 956573c4-74ed-4fc4-b503-08ddf7552cca X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8459.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2025 08:18:55.6113 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hQ4YSfq0woaqLtCHFFIY26QtUqIwd36on8PD+800my886h1iUgeDitDrfXYgQnB/Z9eMjOdH+gR/9w0isXDmSQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI2PR04MB10545 On Fri, Sep 19, 2025 at 09:29:41AM +0200, Michael Walle wrote: >Hi, > >On Thu Sep 18, 2025 at 11:01 AM CEST, Peng Fan wrote: >> On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote: >> >The spi nor on imx8mm evk board works under SDR mode, and >> >driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode. >> >According to the datasheet, there is IO limitation on this chip, >> >the max frequency of such case is 66MHz, so add the limitation >> >here to align with datasheet. >> > >> >Refer to 3.9.10 FlexSPI timing parameters on page 59. >> >https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf >> >> The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports 33MHz and >> 66MHz. Saying the driver now only use RXCLKSRC 0 to restrict the >> device tree to 66MHz is not that correct. >> >> The SoC max frequency could be coded in driver per my understanding. > >Yes that is correct. The spi-max-frequency property is for the >device, not the capabilities of the controller. I.e. the flash chip >on the board. > >> For the QSPI-NOR chip, the spi-max-frequency should represent the NOR chip >> frequency. But that chip supports SDR/DDR, so a new property >> spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR >> CHIP SDR mode frequency? > >Which chip is it? I'm not sure that this is required because the >supported modes might be in the SFDP data and we just support the >8d8d8d mode backed by the JEDEC standard. MT25QU256ABA Clock frequency – 166 MHz (MAX) for all protocols in STR – 90 MHz (MAX) for all protocols in DTR Current spi-max-frequency does not indicate it is STR or DDR. If device tree has spi-max-frequency as 166MHz, but driver configures the working mode as DDR, there might be issues. I not look into details on SFDP or 8d8d8d8d, so my understandings might be wrong. Thanks, Peng > >-michael > >> So if spi-max-frequency is the maximum NOR chip SDR frequency, the driver >> should also be update dthat DDR mode is not supported as of now. >> >> Just my thoughts. >> >> Regards >> Peng. >