[PATCH 1/2] mtd: spi-nor: add configurable RDCR opcode

[Maarten Zanders <maarten@zanders.be>]

Introduce a new flash parameter to hold the read configuration register
(RDCR) opcode. Default to 0x35, which is the JEDEC standard.

This change does not alter existing behavior but prepares the driver
to support flashes that use a different opcode to read the CR.

Fixes: 10526d85e4c6 ("mtd: spi-nor: Move Macronix bits out of core.c")
Signed-off-by: Maarten Zanders <maarten@zanders.be>
---
 drivers/mtd/spi-nor/core.c | 12 +++++++++---
 drivers/mtd/spi-nor/core.h |  6 ++++--
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index ac4b960101cc..ff537bdad401 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -484,7 +484,7 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
 
 /**
  * spi_nor_read_cr() - Read the Configuration Register using the
- * SPINOR_OP_RDCR (35h) command.
+ * SPINOR_OP_RDCR command.
  * @nor:	pointer to 'struct spi_nor'
  * @cr:		pointer to a DMA-able buffer where the value of the
  *              Configuration Register will be written.
@@ -496,13 +496,16 @@ int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
 	int ret;
 
 	if (nor->spimem) {
-		struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
+		struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->params->rdcr_opcode,
+						       cr);
 
 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 
 		ret = spi_mem_exec_op(nor->spimem, &op);
 	} else {
-		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
+		ret = spi_nor_controller_ops_read_reg(nor,
+						      nor->params->rdcr_opcode,
+						      cr,
 						      1);
 	}
 
@@ -2893,6 +2896,9 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
 	/* Default to 16-bit Write Status (01h) Command */
 	nor->flags |= SNOR_F_HAS_16BIT_SR;
 
+	/* Default to 0x35 to read configuration register */
+	params->rdcr_opcode = SPINOR_OP_RDCR;
+
 	/* Set SPI NOR sizes. */
 	params->writesize = 1;
 	params->size = info->size;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index ceff412f7d65..abac5fc45ca8 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -61,8 +61,8 @@
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_DATA_OUT(1, buf, 0))
 
-#define SPI_NOR_RDCR_OP(buf)						\
-	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0),			\
+#define SPI_NOR_RDCR_OP(opcode, buf)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),				\
 		   SPI_MEM_OP_NO_ADDR,					\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_DATA_IN(1, buf, 0))
@@ -351,6 +351,7 @@ struct spi_nor_otp {
  *			in octal DTR mode.
  * @rdsr_addr_nbytes:	dummy address bytes needed for Read Status Register
  *			command in octal DTR mode.
+ * @rdcr_opcode:	opcode needed to read the Configuration Register
  * @n_banks:		number of banks.
  * @n_dice:		number of dice in the flash memory.
  * @die_erase_opcode:	die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE.
@@ -384,6 +385,7 @@ struct spi_nor_flash_parameter {
 	u8				rdsr_addr_nbytes;
 	u8				n_banks;
 	u8				n_dice;
+	u8				rdcr_opcode;
 	u8				die_erase_opcode;
 	u32				*vreg_offset;
 
-- 
2.51.0