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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4db10872687sm1774501cf.28.2025.09.24.17.32.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 17:32:43 -0700 (PDT) From: Wenmeng Liu Date: Thu, 25 Sep 2025 08:32:01 +0800 Subject: [PATCH v4 3/3] media: qcom: camss: tpg: Add TPG support for SA8775P and QCS8300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250925-camss_tpg-v4-3-d2eb099902c8@oss.qualcomm.com> References: <20250925-camss_tpg-v4-0-d2eb099902c8@oss.qualcomm.com> In-Reply-To: <20250925-camss_tpg-v4-0-d2eb099902c8@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758760347; l=16867; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=O/6zUVla7XHxK6GfxbGBH4buhWROnHycn6H4ITMn7AI=; b=UzzATe7ClYaj95iv32f4oR54EfgcbgEKkCxi5rTzj1lDKsqzQJVkWSpmtpydrJda1IW7upW+I 2wgTQehPm3TB2xrmkC1mL2dM4wlXtJWSlCMePAfIhCm7K3CSUzQBOzw X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-GUID: 2hNMh7NQoYSrOhJaDNvox33OpxPNaDdu X-Authority-Analysis: v=2.4 cv=fY2ty1QF c=1 sm=1 tr=0 ts=68d48daf cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=syRLySTArnPnuQ3ofKwA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIyMDE2OCBTYWx0ZWRfX1cMSy34taK+x EsvOcc9kzCVQcJkzfVUtwR49YigomHat3PFY5jCNbdKhkMPYLEC7e0DAt00EpRYCqa9JVK6UHmP cS62atX3w2AtY8JQhsdjGPLmnrVvP8be9nRYkoOkyL0oJ7rDsRb/WbfWZM74xVeaS6mY0yLpIlw ofSjvhJLLou/4CKwyl2BOjuqu8Z2FoNn1tX/tTpryAaK5Z+EcMtTteq9Fi31C4jd7z6mZug5Js5 uV++HXcjp3MTSEvzppqjQWj2+F5RvhABMlfVzgLtHr6utBa+KZWwQSaX3e3ynkBCgWA/b6lA+Cb R+IriPRh8rW9ld/+ASX/RQgNig4FkQzM5Iha2knYk7uHzL4TIgTVo2Qcb/GWrXiXQHzzQiXkKI9 BhIGl8qh X-Proofpoint-ORIG-GUID: 2hNMh7NQoYSrOhJaDNvox33OpxPNaDdu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_07,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509220168 Add support for TPG found on SA8775P and QCS8300. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-gen3.c | 17 ++ drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 219 +++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.c | 79 ++++++++ 4 files changed, 316 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 0eda4b18ad0e93f5e63135fabd5a02ae67bcd5ad..28bc3d9ba16dfa34a8fd35973beed0c3f2b67e00 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -27,5 +27,6 @@ qcom-camss-objs += \ camss-video.o \ camss-format.o \ camss-tpg.o \ + camss-tpg-gen1.o \ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0cac662b02f8b920cd1c72db0aeb2..8e0b0cbaa0010f4b4a156877ac2fe805e5c4422e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -66,6 +66,8 @@ #define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_NUM_EN 27 +#define CSI2_RX_CFG0_TPG_NUM_SEL 28 #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -109,11 +111,26 @@ static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy, int vc) { int val; + struct camss *camss; + struct tpg_device *tpg; + camss = csid->camss; val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL; + if (camss->tpg) { + tpg = &camss->tpg[phy->csiphy_id]; + + if (tpg->testgen.mode > 0) { + val |= (phy->csiphy_id + 1) << CSI2_RX_CFG0_TPG_NUM_SEL; + val |= 1 << CSI2_RX_CFG0_TPG_NUM_EN; + } else { + val |= 0 << CSI2_RX_CFG0_TPG_NUM_SEL; + val |= 0 << CSI2_RX_CFG0_TPG_NUM_EN; + } + } + writel(val, csid->base + CSID_CSI2_RX_CFG0); val = CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c new file mode 100644 index 0000000000000000000000000000000000000000..d0d7ebd710f8cc8ee7005ebc0809d82ece722dff --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG (Test Patter Generator) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +#define TPG_HW_VERSION 0x0 +# define HW_VERSION_STEPPING GENMASK(15, 0) +# define HW_VERSION_REVISION GENMASK(27, 16) +# define HW_VERSION_GENERATION GENMASK(31, 28) + +#define TPG_HW_STATUS 0x4 + +#define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) + +#define TPG_CTRL 0x64 +# define TPG_CTRL_TEST_EN BIT(0) +# define TPG_CTRL_PHY_SEL BIT(3) +# define TPG_CTRL_NUM_ACTIVE_LANES GENMASK(5, 4) +# define TPG_CTRL_VC_DT_PATTERN_ID GENMASK(8, 6) +# define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) +# define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) +# define NUM_ACTIVE_VC_0_ENABLED 0 +# define NUM_ACTIVE_VC_0_1_ENABLED 1 +# define NUM_ACTIVE_VC_0_1_2_ENABLED 2 +# define NUM_ACTIVE_VC_0_1_3_ENABLED 3 + +#define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) +# define TPG_VC_n_CFG0_VC_NUM GENMASK(4, 0) +# define TPG_VC_n_CFG0_NUM_ACTIVE_DT GENMASK(9, 8) +# define NUM_ACTIVE_SLOTS_0_ENABLED 0 +# define NUM_ACTIVE_SLOTS_0_1_ENABLED 1 +# define NUM_ACTIVE_SLOTS_0_1_2_ENABLED 2 +# define NUM_ACTIVE_SLOTS_0_1_3_ENABLED 3 +# define TPG_VC_n_CFG0_NUM_BATCH GENMASK(15, 12) +# define TPG_VC_n_CFG0_NUM_FRAMES GENMASK(31, 16) + +#define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) + +#define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) + +#define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) + +#define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) +# define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN GENMASK(2, 0) +# define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN BIT(3) +# define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN BIT(4) +# define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN BIT(5) +# define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD GENMASK(13, 8) +# define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN BIT(16) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_X GENMASK(26, 24) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y GENMASK(30, 28) + +#define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT GENMASK(15, 0) +# define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_1_DATA_TYPE GENMASK(5, 0) +# define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK GENMASK(13, 8) +# define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE GENMASK(3, 0) +# define TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(27, 4) +# define TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(31, 28) + +#define TPG_VC_n_COLOR_BAR_CFA_COLOR0(n) (0xB0 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR1(n) (0xB4 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR2(n) (0xB8 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR3(n) (0xBC + (n) * 0x60) + +/* Line offset between VC(n) and VC(n-1), n form 1 to 3 */ +#define TPG_VC_n_SHDR_CFG (0x84 + (n) * 0x60) + +#define TPG_CLEAR 0x1F4 + +#define TPG_USER_SPECIFIED_PAYLOAD_DEFAULT 0xBE +#define TPG_HBI_CFG_DEFAULT 0x4701 +#define TPG_VBI_CFG_DEFAULT 0x438 +#define TPG_LFSR_SEED_DEFAULT 0x12345678 +#define TPG_COLOR_BARS_CFG_STANDARD \ + FIELD_PREP(TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD, 0xA) + +static int tpg_stream_on(struct tpg_device *tpg) +{ + struct tpg_testgen_config *tg = &tpg->testgen; + struct v4l2_mbus_framefmt *input_format; + const struct tpg_format_info *format; + u8 lane_cnt = tpg->res->lane_cnt; + u8 dt_cnt = 0; + u8 i; + u32 val; + + /* Loop through all enabled VCs and configure stream for each */ + for (i = 0; i < tpg->res->vc_cnt; i++) { + input_format = &tpg->fmt[MSM_TPG_PAD_SRC + i]; + format = tpg_get_fmt_entry(tpg, + tpg->res->formats->formats, + tpg->res->formats->nformats, + input_format->code); + + val = FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT, input_format->height & 0xffff) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH, input_format->width & 0xffff); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_0(i, dt_cnt)); + + val = FIELD_PREP(TPG_VC_m_DT_n_CFG_1_DATA_TYPE, format->data_type); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_1(i, dt_cnt)); + + val = FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, tg->mode - 1) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, + TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT, format->encode_format); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_2(i, dt_cnt)); + + writel(TPG_COLOR_BARS_CFG_STANDARD, tpg->base + TPG_VC_n_COLOR_BARS_CFG(i)); + + writel(TPG_HBI_CFG_DEFAULT, tpg->base + TPG_VC_n_HBI_CFG(i)); + writel(TPG_VBI_CFG_DEFAULT, tpg->base + TPG_VC_n_VBI_CFG(i)); + + writel(TPG_LFSR_SEED_DEFAULT, tpg->base + TPG_VC_n_LSFR_SEED(i)); + + /* configure one DT, infinite frames */ + val = FIELD_PREP(TPG_VC_n_CFG0_VC_NUM, i) | + FIELD_PREP(TPG_VC_n_CFG0_NUM_FRAMES, 0); + writel(val, tpg->base + TPG_VC_n_CFG0(i)); + } + + val = FIELD_PREP(TPG_CTRL_TEST_EN, 1) | + FIELD_PREP(TPG_CTRL_PHY_SEL, 0) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | + FIELD_PREP(TPG_CTRL_VC_DT_PATTERN_ID, 0) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, tpg->res->vc_cnt - 1); + writel(val, tpg->base + TPG_CTRL); + + return 0; +} + +static void tpg_stream_off(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); +} + +static void tpg_configure_stream(struct tpg_device *tpg, u8 enable) +{ + if (enable) + tpg_stream_on(tpg); + else + tpg_stream_off(tpg); +} + +static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) +{ + if (val > 0 && val <= TPG_PAYLOAD_MODE_COLOR_BARS) + tpg->testgen.mode = val; + + return 0; +} + +/* + * tpg_hw_version - tpg hardware version query + * @tpg: tpg device + * + * Return HW version or error + */ +static u32 tpg_hw_version(struct tpg_device *tpg) +{ + u32 hw_version; + u32 hw_gen; + u32 hw_rev; + u32 hw_step; + + hw_version = readl(tpg->base + TPG_HW_VERSION); + hw_gen = FIELD_GET(HW_VERSION_GENERATION, hw_version); + hw_rev = FIELD_GET(HW_VERSION_REVISION, hw_version); + hw_step = FIELD_GET(HW_VERSION_STEPPING, hw_version); + dev_dbg_once(tpg->camss->dev, "tpg HW Version = %u.%u.%u\n", + hw_gen, hw_rev, hw_step); + + return hw_version; +} + +/* + * tpg_reset - Trigger reset on tpg module and wait to complete + * @tpg: tpg device + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_reset(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); + + return 0; +} + +static void tpg_subdev_init(struct tpg_device *tpg) +{ + tpg->testgen.modes = testgen_payload_modes; + tpg->testgen.nmodes = TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; +} + +const struct tpg_hw_ops tpg_ops_gen1 = { + .configure_stream = tpg_configure_stream, + .configure_testgen_pattern = tpg_configure_testgen_pattern, + .hw_version = tpg_hw_version, + .reset = tpg_reset, + .subdev_init = tpg_subdev_init, +}; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 2ede19e1347ae32f2f6919905b535352bcd134be..dcb99e4eeb9bd9a777e4bc370fa8eff0dd03301f 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2745,6 +2745,62 @@ static const struct camss_subdev_resources csiphy_res_8775p[] = { }, }; +static const struct camss_subdev_resources tpg_res_8775p[] = { + /* TPG0 */ + { + .regulators = { }, + .clock = { "csiphy_rx", "camnoc_axi" }, + .clock_rate = { + { 400000000 }, + { 400000000 }, + }, + .reg = { "tpg0" }, + .interrupt = { "tpg0" }, + .tpg = { + .lane_cnt = 4, + .vc_cnt = 1, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + + /* TPG1 */ + { + .regulators = { }, + .clock = { "csiphy_rx", "camnoc_axi" }, + .clock_rate = { + { 400000000 }, + { 400000000 }, + }, + .reg = { "tpg1" }, + .interrupt = { "tpg1" }, + .tpg = { + .lane_cnt = 4, + .vc_cnt = 1, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + + /* TPG2 */ + { + .regulators = { }, + .clock = { "csiphy_rx", "camnoc_axi" }, + .clock_rate = { + { 400000000 }, + { 400000000 }, + }, + .reg = { "tpg2" }, + .interrupt = { "tpg2" }, + .tpg = { + .lane_cnt = 4, + .vc_cnt = 1, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_8775p[] = { /* CSID0 */ { @@ -4217,6 +4273,13 @@ static int camss_probe(struct platform_device *pdev) if (!camss->csiphy) return -ENOMEM; + if (camss->res->tpg_num > 0) { + camss->tpg = devm_kcalloc(dev, camss->res->tpg_num, + sizeof(*camss->tpg), GFP_KERNEL); + if (!camss->tpg) + return -ENOMEM; + } + camss->csid = devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->csid), GFP_KERNEL); if (!camss->csid) @@ -4350,6 +4413,7 @@ static const struct camss_resources msm8916_resources = { .ispif_res = &ispif_res_8x16, .vfe_res = vfe_res_8x16, .csiphy_num = ARRAY_SIZE(csiphy_res_8x16), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_8x16), .vfe_num = ARRAY_SIZE(vfe_res_8x16), }; @@ -4363,6 +4427,7 @@ static const struct camss_resources msm8953_resources = { .ispif_res = &ispif_res_8x53, .vfe_res = vfe_res_8x53, .csiphy_num = ARRAY_SIZE(csiphy_res_8x96), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_8x53), .vfe_num = ARRAY_SIZE(vfe_res_8x53), }; @@ -4374,6 +4439,7 @@ static const struct camss_resources msm8996_resources = { .ispif_res = &ispif_res_8x96, .vfe_res = vfe_res_8x96, .csiphy_num = ARRAY_SIZE(csiphy_res_8x96), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_8x96), .vfe_num = ARRAY_SIZE(vfe_res_8x96), }; @@ -4386,6 +4452,7 @@ static const struct camss_resources qcm2290_resources = { .icc_res = icc_res_2290, .icc_path_num = ARRAY_SIZE(icc_res_2290), .csiphy_num = ARRAY_SIZE(csiphy_res_2290), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_2290), .vfe_num = ARRAY_SIZE(vfe_res_2290), }; @@ -4394,11 +4461,13 @@ static const struct camss_resources qcs8300_resources = { .version = CAMSS_8300, .pd_name = "top", .csiphy_res = csiphy_res_8300, + .tpg_res = tpg_res_8775p, .csid_res = csid_res_8775p, .csid_wrapper_res = &csid_wrapper_res_sm8550, .vfe_res = vfe_res_8775p, .icc_res = icc_res_qcs8300, .csiphy_num = ARRAY_SIZE(csiphy_res_8300), + .tpg_num = ARRAY_SIZE(tpg_res_8775p), .csid_num = ARRAY_SIZE(csid_res_8775p), .vfe_num = ARRAY_SIZE(vfe_res_8775p), .icc_path_num = ARRAY_SIZE(icc_res_qcs8300), @@ -4408,11 +4477,13 @@ static const struct camss_resources sa8775p_resources = { .version = CAMSS_8775P, .pd_name = "top", .csiphy_res = csiphy_res_8775p, + .tpg_res = tpg_res_8775p, .csid_res = csid_res_8775p, .csid_wrapper_res = &csid_wrapper_res_sm8550, .vfe_res = vfe_res_8775p, .icc_res = icc_res_sa8775p, .csiphy_num = ARRAY_SIZE(csiphy_res_8775p), + .tpg_num = ARRAY_SIZE(tpg_res_8775p), .csid_num = ARRAY_SIZE(csid_res_8775p), .vfe_num = ARRAY_SIZE(vfe_res_8775p), .icc_path_num = ARRAY_SIZE(icc_res_sa8775p), @@ -4425,6 +4496,7 @@ static const struct camss_resources sdm660_resources = { .ispif_res = &ispif_res_660, .vfe_res = vfe_res_660, .csiphy_num = ARRAY_SIZE(csiphy_res_660), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_660), .vfe_num = ARRAY_SIZE(vfe_res_660), }; @@ -4435,6 +4507,7 @@ static const struct camss_resources sdm670_resources = { .csid_res = csid_res_670, .vfe_res = vfe_res_670, .csiphy_num = ARRAY_SIZE(csiphy_res_670), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_670), .vfe_num = ARRAY_SIZE(vfe_res_670), }; @@ -4446,6 +4519,7 @@ static const struct camss_resources sdm845_resources = { .csid_res = csid_res_845, .vfe_res = vfe_res_845, .csiphy_num = ARRAY_SIZE(csiphy_res_845), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_845), .vfe_num = ARRAY_SIZE(vfe_res_845), }; @@ -4459,6 +4533,7 @@ static const struct camss_resources sm8250_resources = { .icc_res = icc_res_sm8250, .icc_path_num = ARRAY_SIZE(icc_res_sm8250), .csiphy_num = ARRAY_SIZE(csiphy_res_8250), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_8250), .vfe_num = ARRAY_SIZE(vfe_res_8250), }; @@ -4473,6 +4548,7 @@ static const struct camss_resources sc8280xp_resources = { .icc_res = icc_res_sc8280xp, .icc_path_num = ARRAY_SIZE(icc_res_sc8280xp), .csiphy_num = ARRAY_SIZE(csiphy_res_sc8280xp), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_sc8280xp), .vfe_num = ARRAY_SIZE(vfe_res_sc8280xp), }; @@ -4486,6 +4562,7 @@ static const struct camss_resources sc7280_resources = { .icc_res = icc_res_sc7280, .icc_path_num = ARRAY_SIZE(icc_res_sc7280), .csiphy_num = ARRAY_SIZE(csiphy_res_7280), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_7280), .vfe_num = ARRAY_SIZE(vfe_res_7280), }; @@ -4500,6 +4577,7 @@ static const struct camss_resources sm8550_resources = { .icc_res = icc_res_sm8550, .icc_path_num = ARRAY_SIZE(icc_res_sm8550), .csiphy_num = ARRAY_SIZE(csiphy_res_8550), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_8550), .vfe_num = ARRAY_SIZE(vfe_res_8550), }; @@ -4514,6 +4592,7 @@ static const struct camss_resources x1e80100_resources = { .icc_res = icc_res_x1e80100, .icc_path_num = ARRAY_SIZE(icc_res_x1e80100), .csiphy_num = ARRAY_SIZE(csiphy_res_x1e80100), + .tpg_num = 0, .csid_num = ARRAY_SIZE(csid_res_x1e80100), .vfe_num = ARRAY_SIZE(vfe_res_x1e80100), }; -- 2.34.1