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[95.249.236.54]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-46e2a9ac5basm98449995e9.7.2025.09.25.08.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Sep 2025 08:53:45 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, upstream@airoha.com Cc: Christian Marangi Subject: [PATCH v3 2/2] PCI: mediatek-gen3: add support for Airoha AN7583 SoC Date: Thu, 25 Sep 2025 17:53:09 +0200 Message-ID: <20250925155330.6779-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250925155330.6779-1-ansuelsmth@gmail.com> References: <20250925155330.6779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for Airoha AN7583 SoC that implement the same logic of Airoha EN7581 with the only difference that only 1 PCIe line is supported (for GEN3). A dedicated compatible is defined with the pdata struct with the 1 reset line. Signed-off-by: Christian Marangi Reviewed-by: AngeloGioacchino Del Regno --- Changes v3: - Add review tag Changes v2: - Fix alphabetical order drivers/pci/controller/pcie-mediatek-gen3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 75ddb8bee168..6e68ed75b564 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1360,7 +1360,17 @@ static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { .flags = SKIP_PCIE_RSTB, }; +static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_an7583 = { + .power_up = mtk_pcie_en7581_power_up, + .phy_resets = { + .id[0] = "phy-lane0", + .num_resets = 1, + }, + .flags = SKIP_PCIE_RSTB, +}; + static const struct of_device_id mtk_pcie_of_match[] = { + { .compatible = "airoha,an7583-pcie-gen3", .data = &mtk_pcie_soc_an7583 }, { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, { .compatible = "mediatek,mt8196-pcie", .data = &mtk_pcie_soc_mt8196 }, -- 2.51.0