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Tue, 30 Sep 2025 05:38:41 -0700 (PDT) Received: from ziepe.ca ([130.41.10.202]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4e34ef75712sm8696611cf.7.2025.09.30.05.38.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Sep 2025 05:38:40 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1v3Zct-0000000CWSm-3Tg2; Tue, 30 Sep 2025 09:38:39 -0300 Date: Tue, 30 Sep 2025 09:38:39 -0300 From: Jason Gunthorpe To: Mostafa Saleh Cc: Will Deacon , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, mark.rutland@arm.com, praan@google.com Subject: Re: [PATCH v4 10/28] KVM: arm64: iommu: Shadow host stage-2 page table Message-ID: <20250930123839.GL2695987@ziepe.ca> References: <20250819215156.2494305-1-smostafa@google.com> <20250819215156.2494305-11-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Sep 29, 2025 at 11:01:10AM +0000, Mostafa Saleh wrote: > > If the SMMU is in stage-1 bypass, we still have the incoming memory > > attributes from the transaction (modulo MTCFG which we shouldn't be > > setting) and they should combine with the stage-2 attributes in roughly > > the same way as the CPU, no? > > Makes sense, we can remove that for now and map all stage-2 with > IOMMU_CACHE. Robin was saying in another thread that the DMA API has to use IOMMU_MMIO properly or it won't work.. I think what happens depends on the SOC design. Yes, the incoming attribute combines, but unlike the CPU which will have per-page memory attributes in the S1, the DMA initiator will almost always use the same memory attributes. In other words, we cannot rely on the DMA initiator to indicate if the underlying memory should be MMIO or CACHE like the CPU can. I think you have to set CACHE/MMIO correctly here. Jason