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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2025 06:19:13.8298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f42e40f2-62ee-4caf-8fc9-08de0244c628 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9408 This patch series addresses issues and optimizations in the Xilinx AXI DMA and MCDMA drivers: 1. Fix channel idle state management in the interrupt handlers. 2. Enable transfer chaining by removing unnecessary idle restrictions. 3. Optimize control register writes and channel start logic. Note: The patches in this series were part of following IRQ coalescing series which is under discussion: https://lore.kernel.org/all/20250710101229.804183-1-suraj.gupta2@amd.com/ Changes in V2: - Apply similar fixes and optimizations to MCDMA as well. - Expand the 1/3 commit description with when the described issue occurs. Suraj Gupta (3): dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers dmaengine: xilinx_dma: Enable transfer chaining for AXIDMA and MCDMA by removing idle restriction dmaengine: xilinx_dma: Optimize control register write and channel start logic for AXIDMA and MCDMA in corresponding start_transfer() drivers/dma/xilinx/xilinx_dma.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 2.25.1