From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <jgg@nvidia.com>, <nicolinc@nvidia.com>
Cc: <linux-kernel@vger.kernel.org>, <robin.murphy@arm.com>,
<will@kernel.org>, <joro@8bytes.org>, <kevin.tian@intel.com>,
<jsnitsel@redhat.com>, <vasant.hegde@amd.com>,
<iommu@lists.linux.dev>, <santosh.shukla@amd.com>,
<sairaj.arunkodilkar@amd.com>, <jon.grimm@amd.com>,
<prashanthpra@google.com>, <wvw@google.com>, <wnliu@google.com>,
<gptran@google.com>, <kpsingh@google.com>,
<joao.m.martins@oracle.com>, <alejandro.j.jimenez@oracle.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PATCH v3 14/15] iommu/amd: Refactor logic to program the host page table in DTE
Date: Thu, 9 Oct 2025 23:57:54 +0000 [thread overview]
Message-ID: <20251009235755.4497-15-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20251009235755.4497-1-suravee.suthikulpanit@amd.com>
Introduce the set_dte_v1() helper function to configure IOMMU host (v1)
page table into DTE.
There is no functional change.
Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/iommu.c | 54 +++++++++++++++++++++------------------
1 file changed, 29 insertions(+), 25 deletions(-)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index ffb1adfd75c0..2a536d02aeab 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2044,6 +2044,32 @@ static void set_dte_gcr3_table(struct amd_iommu *iommu,
target->data[2] |= FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_4_LEVEL);
}
+static void set_dte_v1(struct iommu_dev_data *dev_data,
+ struct protection_domain *domain, u16 domid,
+ struct dev_table_entry *new)
+{
+ /*
+ * When SNP is enabled, we can only support TV=1 with non-zero domain ID.
+ * This is prevented by the SNP-enable and IOMMU_DOMAIN_IDENTITY check in
+ * do_iommu_domain_alloc().
+ */
+ WARN_ON(amd_iommu_snp_en && (domid == 0));
+
+ if (domain->iop.mode != PAGE_MODE_NONE)
+ new->data[0] |= iommu_virt_to_phys(domain->iop.root);
+
+ new->data[0] |= FIELD_PREP(DTE_MODE_MASK, domain->iop.mode);
+ new->data[0] |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV;
+
+ if (domain->dirty_tracking)
+ new->data[0] |= DTE_FLAG_HAD;
+
+ if (dev_data->ats_enabled)
+ new->data[1] |= DTE_FLAG_IOTLB;
+
+ new->data[1] |= domid;
+}
+
static void set_dte_entry(struct amd_iommu *iommu,
struct iommu_dev_data *dev_data)
{
@@ -2061,36 +2087,14 @@ static void set_dte_entry(struct amd_iommu *iommu,
amd_iommu_make_clear_dte(dev_data, &new);
- if (domain->iop.mode != PAGE_MODE_NONE)
- new.data[0] |= iommu_virt_to_phys(domain->iop.root);
-
- new.data[0] |= (domain->iop.mode & DEV_ENTRY_MODE_MASK)
- << DEV_ENTRY_MODE_SHIFT;
-
- new.data[0] |= DTE_FLAG_IR | DTE_FLAG_IW;
+ old_domid = READ_ONCE(dte->data[1]) & DTE_DOMID_MASK;
- /*
- * When SNP is enabled, we can only support TV=1 with non-zero domain ID.
- * This is prevented by the SNP-enable and IOMMU_DOMAIN_IDENTITY check in
- * do_iommu_domain_alloc().
- */
- WARN_ON(amd_iommu_snp_en && (domid == 0));
- new.data[0] |= DTE_FLAG_TV;
+ set_dte_v1(dev_data, domain, domid, &new);
+ set_dte_gcr3_table(iommu, dev_data, &new);
if (dev_data->ppr)
new.data[0] |= 1ULL << DEV_ENTRY_PPR;
- if (domain->dirty_tracking)
- new.data[0] |= DTE_FLAG_HAD;
-
- if (dev_data->ats_enabled)
- new.data[1] |= DTE_FLAG_IOTLB;
-
- old_domid = READ_ONCE(dte->data[1]) & DTE_DOMID_MASK;
- new.data[1] |= domid;
-
- set_dte_gcr3_table(iommu, dev_data, &new);
-
amd_iommu_update_dte256(iommu, dev_data, &new);
/*
--
2.34.1
next prev parent reply other threads:[~2025-10-09 23:59 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 23:57 [PATCH v3 00/15] iommu/amd: Introduce Nested Translation support Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 01/15] iommu/amd: Rename DEV_DOMID_MASK to DTE_DOMID_MASK Suravee Suthikulpanit
2025-10-13 10:51 ` Sairaj Kodilkar
2025-10-14 2:08 ` Suthikulpanit, Suravee
2025-10-09 23:57 ` [PATCH v3 02/15] iommu/amd: Make amd_iommu_pdom_id_alloc() non-static Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 03/15] iommu/amd: Make amd_iommu_pdom_id_free() non-static Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 04/15] iommu/amd: Make amd_iommu_device_flush_dte() non-static Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 05/15] iommu/amd: Make amd_iommu_update_dte256() non-static Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 06/15] iommu/amd: Make amd_iommu_make_clear_dte() non-static inline Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 07/15] iommu/amd: Make amd_iommu_completion_wait() non-static Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 08/15] iommufd: Introduce data struct for AMD nested domain allocation Suravee Suthikulpanit
2025-10-09 23:57 ` [PATCH v3 09/15] iommu/amd: Always enable GCR3TRPMode when supported Suravee Suthikulpanit
2025-10-10 22:37 ` Jason Gunthorpe
2025-10-09 23:57 ` [PATCH v3 10/15] iommu/amd: Add support for nest parent domain allocation Suravee Suthikulpanit
2025-10-10 22:38 ` Jason Gunthorpe
2025-10-09 23:57 ` [PATCH v3 11/15] iommu/amd: Add support for nested " Suravee Suthikulpanit
2025-10-10 22:54 ` Jason Gunthorpe
2025-10-09 23:57 ` [PATCH v3 12/15] iommu/amd: Validate guest DTE for nested translation Suravee Suthikulpanit
2025-10-10 22:55 ` Jason Gunthorpe
2025-10-09 23:57 ` [PATCH v3 13/15] iommu/amd: Refactor persistent DTE bits programming into amd_iommu_make_clear_dte() Suravee Suthikulpanit
2025-10-10 22:56 ` Jason Gunthorpe
2025-10-09 23:57 ` Suravee Suthikulpanit [this message]
2025-10-10 23:09 ` [PATCH v3 14/15] iommu/amd: Refactor logic to program the host page table in DTE Jason Gunthorpe
2025-10-21 1:26 ` Suthikulpanit, Suravee
2025-10-09 23:57 ` [PATCH v3 15/15] iommu/amd: Add support for nested domain attach/detach Suravee Suthikulpanit
2025-10-10 23:20 ` Jason Gunthorpe
2025-10-20 23:17 ` Suthikulpanit, Suravee
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