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Mon, 13 Oct 2025 13:51:40 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([145.224.67.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fab3e3206sm133512615e9.4.2025.10.13.13.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 13:51:40 -0700 (PDT) From: Peter Griffin Subject: [PATCH 0/9] Implement hardware automatic clock gating (HWACG) for gs101 Date: Mon, 13 Oct 2025 21:51:29 +0100 Message-Id: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAFFm7WgC/x3MQQ5AMBBA0avIrDWpBsFVxKLGYIJW2hKJ9O4ay 7f4/wVPjslDl73g6GbP1iQUeQa4arOQ4CkZlFRVIWUj9BXsoQOjwN3i5oUqWz3Wcq4VEqTsdDT z8y/7IcYP21AcqmIAAAA= X-Change-ID: 20251008-automatic-clocks-249ab60f62ce To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Hi folks, This series addresses an issue with Samsung Exynos based upstream clock driver whereby the upstream clock driver sets all the clock gates into "manual mode" (which uses a bit that is documented as reserved in the gate registers). Another issue with the current "manual clock gating" approach upstream is there are many bus/interconnect clocks whose relationships to the IPs are not well documented or defined in the specs. When adding a new CMU until now we have tried to label these clocks appropriately with CLK_IS_CRITICAL and CLK_IGNORE_UNUSED but doing so is both error prone and time consuming. If your lucky disabling a critical bus clock causes an immediate hang. Other clocks however aren't so obvious and show up through random instability some period of time later. Fortunately each CMU (at least on newer Exynos) provides a "hardware automatic clock gating" HWACG feature that is used by the downstream Samsung clock drivers. Hardware automatic clock gating uses a hardware interface between the CMU and IP to control all clocks required by the IP. This interface is called Q-channel, and is part of the Arm AMBA low power interface specification [1]. The advantage of using this Qchannel hardware interface for enabling/disabling the clocks is that it takes care of all clocks (including bus/interconnect) ones for the IP automatically thereby reducing the dynamic power. Whilst each clock component (GATE, MUX, DIV, QCH etc) has a HWACG enable bit there are also some "global enable override" bits for the entire CMU in the CMU_CONTROLLER_OPTION register. This series makes use of those "global enable" override bits to enable auto clock mode for the entire CMU and every component within it. Through experimentation we can see that setting the "manual mode" reserved gate bit on a particular gate register overides the global enable bits. So the code is updated accordingly not to do that. Auto clock mode has been implemented as a "opt in" by setting a new auto_clock_gate flag in the CMU static data. The intention is existing platforms in manual mode should not be effected by any of these changes. If auto_clock_mode flag is set and the option_offset field is specified then the global enable override bits will be written for the CMU (to avoid relying on any prior bootstage configuration). Again if auto mode is enabled the code no longer sets MANUAL and clears HWACG bits on each gate register. To have dynamic root clock gating (drcg) of bus components and memclk enabled, it is required to set the bus_component_drcg and memclk registers in the the correspondingly named sysreg controller. If auto clock mode is enabled the clock driver will now attempt to get the sysreg syscon via the samsung,sysreg property (as used by other Exynos drivers upstream) and set the registers accordingly. The suspend/resume code paths are also updated to handle saving/restoring registers using a regmap. Note cmu_top is an exception and does not have a corresondingly named sysreg_top. As all clock gates are currently exposed in the gs101 drivers and DT, we continue to register all of these gates in auto clock mode, but with some new samsung_auto_clk_gate_ops. As clk enable and clk disable are now handled by Q-channel interface the .enable and .disable implementations are no-ops. However by using some CMU qchannel debug registers we can report the current clock status (enabled or disabled) of every clock gate in the system. This has the nice effect of still being able to dump the entire clock tree from /sys/kernel/debug/clk/clk_summary and see a live view of every auto clock in the system. With the infrastructure in place, all the CMUs registerred in clk-gs101 are now updated to enable auto clock mode. From dumping /sys/kernel/debug/clk/clk_summary it is possible to see that after enabling auto clock mode approximately 305 clocks are enabled, and 299 are now disabled. This number goes up and down a bit by 3-5 clocks just on a idle system sat at a console. As the CLK_IGNORE_UNUSED and CLK_IS_CRITICAL flags lose any meaning in auto clock mode they are removed. It is now also possible to boot without the clk_ignore_unused kernel command line property for the first time! Prior to enabling auto clock mode 586 clocks were enabled, and 17 disabled (in part due to having to boot with clk_ignore_unused flag). To ensure compatability with older DTs the resource size is now checked and an error issued if the DT needs updating to be compatible with auto clock mode. For future CMUs in gs101 I propose we continue to expose all gates, but register the CMU in "auto mode". For new device drivers or updates to existing dt bindings related to clocks to support gs101 I suggest we only use the "obviously correct" clock(s). By "obviously correct" I mean a clock has the IP name in the clock register name, but not try to deduce other obsucurely named bus/interconnect clocks which will now all be handled automatically. Note it is still possible to test whether the "obviously correct" clock is indeed correct by putting the individual gate in manual mode and disabling the clock (e.g. by using devmem). Note: As everything here will go via one of Krzysztof's trees I've sent it as one series. regards, Peter [1] https://documentation-service.arm.com/static/5f915e69f86e16515cdc3b3e?token= Signed-off-by: Peter Griffin --- Peter Griffin (9): dt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatibles dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required arm64: dts: exynos: gs101: add sysreg_misc and sysreg_hsi0 nodes arm64: dts: exynos: gs101: fix clock module unit reg sizes arm64: dts: exynos: gs101: fix sysreg_apm reg property arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes clk: samsung: Implement automatic clock gating mode for CMUs clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU clk: samsung: gs101: remove CLK_IGNORE_UNUSED and CLK_IS_CRITICAL flags .../bindings/clock/google,gs101-clock.yaml | 23 ++- .../soc/samsung/samsung,exynos-sysreg.yaml | 4 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 +++-- drivers/clk/samsung/clk-exynos-arm64.c | 47 +++++- drivers/clk/samsung/clk-exynos4.c | 6 +- drivers/clk/samsung/clk-exynos4412-isp.c | 4 +- drivers/clk/samsung/clk-exynos5250.c | 2 +- drivers/clk/samsung/clk-exynos5420.c | 4 +- drivers/clk/samsung/clk-gs101.c | 167 ++++++++++++++------- drivers/clk/samsung/clk.c | 161 ++++++++++++++++++-- drivers/clk/samsung/clk.h | 49 +++++- 11 files changed, 412 insertions(+), 91 deletions(-) --- base-commit: 4a71531471926e3c391665ee9c42f4e0295a4585 change-id: 20251008-automatic-clocks-249ab60f62ce Best regards, -- Peter Griffin