From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 752F931CA42 for ; Wed, 15 Oct 2025 10:52:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760525574; cv=none; b=nDefMNt/4QrLYQoXqNAagsO6/nWRmxK2bEhNoaG1QMf2bqIcXfJbnhViBc03lcu88grmkSI2auvzhimpH24SCfHpQATIQXf6vBLrAxElfCXd3JoHL6fnfNU11PPOxrHQ8WxX5fZNdrGfPNYbBlc1+e5NOfceznwe/YwmucO4PbY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760525574; c=relaxed/simple; bh=Z57KOB9v07tyf67GGhWybCGCn3jlFYAJ0YHv/BzThyg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fNldL4AU7bnKGzuDqAxDn+Da0lnP4fdghlMGgEnq/4gtd8ltIDZjG8KINYXNPfSGnAU1CVu9WsiQMgymccUCVC/1/gAr7Fv5P+CySleKwlFxHbJFk5pujvlXr66LdE+VS00e7I3SscADRjlJ1DC6Qo69rS0r3xv7zOZxE7dJOw4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=DjAZRudR; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="DjAZRudR" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 59FAWJEN004000 for ; Wed, 15 Oct 2025 10:52:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=+B4kDtQUTGp VB7yyKrf8cwzmgvz1UyvN6sxfACa3DWo=; b=DjAZRudRfz9ZHC9lDnWWQUgzhUF /NGSj770jQj6/C5bvf19XCkiS5F/MFemeakS5+++iuGAP7WGsCEZj8ik/RPd/+yM RmqE5HU5HmQM02zjA1/u24TQdAu/nQPB9ppennO07AULejsJPdZWTL0Db0YWemK/ EGNsEw7zWzeuabHWEWwOnAFa7y4B965d5H2EkmjrOWhtKIQj51qbZQ5Sfm5WeHNu DLGwh7NVWYflcmIEWauGSJDv/wuCJOHo6AUYfeIi1qRqGVkO2MKu2+aYUfyErF5m XVdrzYoHyefNSatN8NwyzVsYvpVbh76NSYdtaZKyU/iv6Ne2bZuur5loOKw== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 49s6mwpdpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 15 Oct 2025 10:52:51 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-29076e11974so21909285ad.3 for ; Wed, 15 Oct 2025 03:52:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760525571; x=1761130371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+B4kDtQUTGpVB7yyKrf8cwzmgvz1UyvN6sxfACa3DWo=; b=gqAawSXh6eFWpNaNNgJovwLiviYWHb6s1LoZF8eYlWi+oB6lACAnhtW2LIyin5WdBS tauyhIChlvXtbJI1SRCoiuX4ErnyfCUJCxCqFu8G8iL3rzX2BdkO2vfZVJuDsul9XTqH fVmtUDRwp0XvDFzAXjtB+Zc+ljIIdlUjnKeH5LgcXFUZm2eaJso3MxS+m1+KP9ErVqen xgA/7ZaCQTY6vWzDXwCyfJOcso0KnF4A8CmjlXMLcISDzfy52leyIHvdrmkrMIZUOO+7 Tx1t7xR1fNmkXXQ4VdC7417HF6MZ8O4cShFk/j9Zn1fWQ3BR8pbeAQi0aDegIslxQxkr N2xQ== X-Forwarded-Encrypted: i=1; AJvYcCUVJxVIB2y+L6yLa+Hv27prN4AwzBp33LknnyGCl3pmVt/rGvQvD7Y7XI4Pl7EDEby1jHOIsiVGb5ZcFGk=@vger.kernel.org X-Gm-Message-State: AOJu0YxWM4IusflmBLAs7nA8jQ1VqVzyRBdDWNFC9mHLY4EFWj3kQs45 5mDYYClJkfK6EBy10mP+QDO6w6/IY0PHpje2ajWaqIydhY8iPC1qsSk/CzApwnx1PRCat3YTX+j zXoQqli2bZCWDBd1f/P3H1dr/EGNcd8+M1dacgIImUwxzIAU4oEfztJT0z7lYP3fpE10= X-Gm-Gg: ASbGncsfscQDpOJPjdgNDI3TGYCsxASoUSp0ufxA1pEmbNUxXgLYEjjKJorkbMt6iCz 5/rcyxBzyF2nYnNfXXbfZO4J2v/K4+cgeI20lyVPLpoVVnLrNrox7oEzwB+FYwUEEheBLKrnJx2 DSVM9gXZFtdOkijbJxAbW9GFt46gxBR9jC10APKG7PQEdYT72+z9nl8/kODERMhNsTIvhq58pyo J0ChuJEcv+l1/kCtvcifbSFc2gqVbw35nkQiLPgojKfKYKHgQWcWfBjbwF9rL8Jqa6eK/+Ku9me UtlUYqcLuiwMLO2/3UE2cnNC7Km0sd71ZFTb3xuTfzbdkl+SWkf90mBYAbResUheiEZ7GVAwvyn Klw== X-Received: by 2002:a17:902:fc4d:b0:269:82a5:f9e9 with SMTP id d9443c01a7336-290272c0729mr359928115ad.29.1760525570622; Wed, 15 Oct 2025 03:52:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEAL49nIZ0DFxVSPXrbRzyokYm6KZnds4ACzmtHvgVr5wMS2b48aVakH+lR6BKp7MfQPL0YEg== X-Received: by 2002:a17:902:fc4d:b0:269:82a5:f9e9 with SMTP id d9443c01a7336-290272c0729mr359927785ad.29.1760525570140; Wed, 15 Oct 2025 03:52:50 -0700 (PDT) Received: from hu-kriskura-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034e20f8csm193698385ad.49.2025.10.15.03.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Oct 2025 03:52:49 -0700 (PDT) From: Krishna Kurapati To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Geert Uytterhoeven , Arnd Bergmann , Nishanth Menon , Eric Biggers , nfraprado@collabora.com, Lad Prabhakar , Kuninori Morimoto Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wesley Cheng , Konrad Dybcio , Dmitry Baryshkov , Krzysztof Kozlowski , Melody Olvera , Krishna Kurapati Subject: [PATCH v7 1/4] arm64: dts: qcom: sm8750: Add USB support to SM8750 SoCs Date: Wed, 15 Oct 2025 16:22:28 +0530 Message-Id: <20251015105231.2819727-2-krishna.kurapati@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251015105231.2819727-1-krishna.kurapati@oss.qualcomm.com> References: <20251015105231.2819727-1-krishna.kurapati@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDEzMDA4MyBTYWx0ZWRfX4iIYVu4gF3qU J6OOO7xlxHP42tiarADxtFEhBBaYfpgh5Hs9x1rbd4LedMRT9GkeJNEtGxeojyu6/GNmDNveMxG bdRyd3V8G+e4uVre795AZC2AtOYP7wNBOxBegFxyVHzT+iwvRzKMUuFA7ELZNwfo/e/PnMHcIrw c+mKBQ3OywMBM2W+FzHtKq/GE9BFUEgBBQEudIBQE/7+ME/uhU3r1AriG8XV2Z9xxGNJ8s94MGp LTQ/1NaOqOLo9pEK/7iZYbV4dqNkSCVqOohf1R8vfs7pkmfhbrWAKSPsKcPFJOAekL5oHzJLw7t u3PFko10yOQURS/FjUJO2Wc+QZKlroPLkct4Ziuvchl7MfPUzM7rvc208+40IAVcRjqeOeg0wIQ 5tGPe+ZYLC7XgUcyJn40Km5ER7FWDg== X-Authority-Analysis: v=2.4 cv=Fr4IPmrq c=1 sm=1 tr=0 ts=68ef7d03 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=n1SQX4eW7R_9Zp26JX0A:9 a=324X-CrmTo6CU4MGRt3R:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 3Mjt8k-yMrFszOAC6uXJjJu04msF01_7 X-Proofpoint-ORIG-GUID: 3Mjt8k-yMrFszOAC6uXJjJu04msF01_7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-15_04,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510130083 From: Wesley Cheng Add the base USB devicetree definitions for SM8750 platforms. The overall chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. The major difference for SM8750 is the transition to using the M31 eUSB2 PHY compared to previous SoCs. Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 164 +++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index a82d9867c7cb..450fe5b7f03e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -2581,6 +2582,169 @@ data-pins { }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x88e3000 0x0 0x29c>; + + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8750-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8750-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xe000>; + + interrupts = ; + + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; -- 2.34.1