Re: [PATCH v2 3/5] clk: rockchip: Add clock controller for the RV1126B

[kernel test robot <lkp@intel.com>]

Hi Elaine,

kernel test robot noticed the following build errors:

[auto build test ERROR on rockchip/for-next]
[also build test ERROR on clk/clk-next pza/reset/next linus/master v6.18-rc1 next-20251017]
[cannot apply to pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Elaine-Zhang/clk-rockchip-Implement-rockchip_clk_register_armclk_multi_pll/20251017-180259
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
patch link:    https://lore.kernel.org/r/20251017063107.1606965-4-zhangqing%40rock-chips.com
patch subject: [PATCH v2 3/5] clk: rockchip: Add clock controller for the RV1126B
config: arm-multi_v7_defconfig (https://download.01.org/0day-ci/archive/20251019/202510191337.86OcUAWo-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251019/202510191337.86OcUAWo-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510191337.86OcUAWo-lkp@intel.com/

All errors (new ones prefixed by >>):

   arm-linux-gnueabi-ld: drivers/clk/rockchip/clk-rv1126b.o: in function `rv1126b_clk_init':
>> drivers/clk/rockchip/clk-rv1126b.c:1050:(.init.text+0xc8): undefined reference to `rk3576_rst_init'


vim +1050 drivers/clk/rockchip/clk-rv1126b.c

  1012	
  1013	static struct rockchip_clk_branch rv1126b_armclk __initdata =
  1014		MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
  1015				RV1126B_CORECLKSEL_CON(0), 1, 1, MFLAGS);
  1016	
  1017	static void __init rv1126b_clk_init(struct device_node *np)
  1018	{
  1019		struct rockchip_clk_provider *ctx;
  1020		void __iomem *reg_base;
  1021		unsigned long clk_nr_clks;
  1022	
  1023		clk_nr_clks = rockchip_clk_find_max_clk_id(rv1126b_clk_branches,
  1024							   ARRAY_SIZE(rv1126b_clk_branches)) + 1;
  1025	
  1026		reg_base = of_iomap(np, 0);
  1027		if (!reg_base) {
  1028			pr_err("%s: could not map cru region\n", __func__);
  1029			return;
  1030		}
  1031	
  1032		ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
  1033		if (IS_ERR(ctx)) {
  1034			pr_err("%s: rockchip clk init failed\n", __func__);
  1035			iounmap(reg_base);
  1036			return;
  1037		}
  1038	
  1039		rockchip_clk_register_plls(ctx, rv1126b_pll_clks,
  1040					   ARRAY_SIZE(rv1126b_pll_clks),
  1041					   RV1126B_GRF_SOC_STATUS0);
  1042	
  1043		rockchip_clk_register_branches(ctx, rv1126b_clk_branches,
  1044					       ARRAY_SIZE(rv1126b_clk_branches));
  1045	
  1046		rockchip_clk_register_armclk_multi_pll(ctx, &rv1126b_armclk,
  1047						       rv1126b_cpuclk_rates,
  1048						       ARRAY_SIZE(rv1126b_cpuclk_rates));
  1049	
> 1050		rk3576_rst_init(np, reg_base);
  1051	
  1052		rockchip_register_restart_notifier(ctx, RV1126B_GLB_SRST_FST, NULL);
  1053	
  1054		rockchip_clk_of_add_provider(np, ctx);
  1055	
  1056		/* pvtpll src init */
  1057		writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_CORECLKSEL_CON(0));
  1058		writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_NPUCLKSEL_CON(0));
  1059		writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VICLKSEL_CON(0));
  1060		writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VEPUCLKSEL_CON(0));
  1061		writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VCPCLKSEL_CON(0));
  1062	}
  1063	

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