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Sun, 19 Oct 2025 21:25:36 -0700 (PDT) From: Xu Lu To: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com, anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com, shuah@kernel.org, parri.andrea@gmail.com, ajones@ventanamicro.com, brs@rivosinc.com, guoren@kernel.org Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, apw@canonical.com, joe@perches.com, lukas.bulwahn@gmail.com, Xu Lu Subject: [PATCH v4 08/10] riscv: Remove arch specific __atomic_acquire/release_fence Date: Mon, 20 Oct 2025 12:24:55 +0800 Message-ID: <20251020042457.30915-4-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251020042457.30915-1-luxu.kernel@bytedance.com> References: <20251020042457.30915-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Remove arch specific __atomic_acquire/release_fence() operations since they use fence instruction to simulate acquire/release order and can not work well with real acquire/release instructions. The default generic __atomic_acuire/release_fence() now provide sequential order via 'fennce rw, rw'. They are rarely called since we use real acquire/release instructions in most of times. Signed-off-by: Xu Lu --- arch/riscv/include/asm/atomic.h | 6 ------ arch/riscv/include/asm/fence.h | 4 ---- 2 files changed, 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 86291de07de62..6ed50a283bf8b 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -18,12 +18,6 @@ #include -#define __atomic_acquire_fence() \ - __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") - -#define __atomic_release_fence() \ - __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); - static __always_inline int arch_atomic_read(const atomic_t *v) { return READ_ONCE(v->counter); diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 182db7930edc2..9ce83e4793948 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -7,12 +7,8 @@ ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r, rw) -#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw, w) #define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw, rw) #else -#define RISCV_ACQUIRE_BARRIER -#define RISCV_RELEASE_BARRIER #define RISCV_FULL_BARRIER #endif -- 2.20.1