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Thu, 23 Oct 2025 07:01:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFU9Vc6znRHA5p61MvlM1lauESPJdCT96hHFW7bW4s6ZjQp41JGsdZDFlOF51ydY6xFUR63lw== X-Received: by 2002:a05:600c:5493:b0:46e:3dad:31ea with SMTP id 5b1f17b1804b1-475cafcaee8mr17241025e9.17.1761228062893; Thu, 23 Oct 2025 07:01:02 -0700 (PDT) Received: from holism.Home ([2a06:5900:814a:ab00:c1c7:2e09:633d:e94e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429898add96sm4116154f8f.30.2025.10.23.07.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Oct 2025 07:01:02 -0700 (PDT) From: Lucas Zampieri To: linux-kernel@vger.kernel.org Cc: Lucas Zampieri , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Vivian Wang , Charles Mirabile , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v6 0/4] Add UltraRISC DP1000 PLIC support Date: Thu, 23 Oct 2025 15:00:49 +0100 Message-ID: <20251023140057.204439-1-lzampier@redhat.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds support for the PLIC implementation in the UltraRISC DP1000 SoC. The UR-CP100 cores used in the DP1000 have a hardware bug in their PLIC claim register where reading it while multiple interrupts are pending can return the wrong interrupt ID. The workaround temporarily disables all interrupts except the first pending one before reading the claim register, then restores the previous state. The driver matches on "ultrarisc,cp100-plic" (CPU core compatible), allowing the quirk to apply to all SoCs using UR-CP100 cores (currently DP1000, potentially future SoCs). Charles Mirabile (3): dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC irqchip/plic: enable optimization of interrupt enable state irqchip/plic: add support for UltraRISC DP1000 PLIC Lucas Zampieri (1): dt-bindings: vendor-prefixes: add UltraRISC Changes in v6: - Split enable_save optimization into separate patch 0003 - 0003: New patch - Optimize interrupt enable state tracking by maintaining enable_save during normal operation instead of only during suspend/resume - 0004: Use existing enable_save[] instead of reading enable registers before workaround - 0004: Return iso_mask from cp100_isolate_pending_irq to use in restore logic - 0004: Skip writing enable masks that haven't changed during isolation - 0004: Skip restoring enable masks that haven't changed after claim - 0004: Skip checking groups with no enabled interrupts in cp100_isolate_pending_irq - 0004: Updated commit message to clarify dependency on enable_save optimization Changes in v5: - 0004: Added brackets around conditional in cp100_isolate_pending_irq (feedback from Thomas Gleixner) - 0004: Reordered variables in reverse fir tree order in cp100_get_hwirq (feedback from Thomas Gleixner) - 0004: Replaced raw_spin_lock/unlock with guard(raw_spinlock) (feedback from Thomas Gleixner) - 0004: Added newline between variable declaration and code in plic_probe (feedback from Thomas Gleixner) - 0004: Extended generic_handle_domain_irq call to single line (feedback from Thomas Gleixner) Changes in v4: - 0002: Simplified commit message to focus on hardware bug (feedback from Conor Dooley) - 0002: Added Conor's Acked-by - 0004: Renamed PLIC_QUIRK_CLAIM_REGISTER to PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM to be more specific (feedback from Samuel Holland) - 0004: Added Samuel's Acked-by Changes in v3: - 0002: Updated commit message to clarify that DP1000 is an SoC and CP100 is a core (feedback from Conor Dooley) - 0004: Renamed dp1000_* functions to cp100_* and updated commit message to clarify the hardware bug is in the UR-CP100 core implementation, not specific to the DP1000 SoC - 0004: Moved quirk check out of hot interrupt path by creating separate plic_handle_irq_cp100() function and selecting handler at probe time - 0004: Use existing handler->enable_save[] array instead of stack allocation - 0004: Use readl_relaxed()/writel_relaxed() for better performance Changes in v2: - 0002: Changed compatible string pattern to SoC+core: ultrarisc,dp1000-plic with ultrarisc,cp100-plic fallback (suggested by Krzysztof and Vivian) - 0004: Driver now matches on ultrarisc,cp100-plic (core) instead of dp1000 (SoC) - All patches: Added submitter Signed-off-by to complete DCO chain .../sifive,plic-1.0.0.yaml | 3 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/irqchip/irq-sifive-plic.c | 126 +++++++++++++++++-- 3 files changed, 118 insertions(+), 10 deletions(-) -- 2.51.0