From: Roger Quadros <rogerq@kernel.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Russell King <linux@armlinux.org.uk>,
danishanwar@ti.com
Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, Roger Quadros <rogerq@kernel.org>
Subject: [PATCH net-next v5 9/9] net: ethernet: ti: am65-cpsw: remove cpsw_ale_classifier_setup_default()
Date: Fri, 24 Oct 2025 23:46:08 +0300 [thread overview]
Message-ID: <20251024-am65-cpsw-rx-class-v5-9-c7c2950a2d25@kernel.org> (raw)
In-Reply-To: <20251024-am65-cpsw-rx-class-v5-0-c7c2950a2d25@kernel.org>
The RX classifier can now be configured by user using ethtool -N.
So drop cpsw_ale_classifier_setup_default().
The default behaviour is that all RX traffic is routed to channel 0.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 --
drivers/net/ethernet/ti/cpsw_ale.c | 52 --------------------------------
drivers/net/ethernet/ti/cpsw_ale.h | 1 -
3 files changed, 56 deletions(-)
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index 1466cf5706c911ede9e03d53f58af83c24a66544..366b70fc79726fa7ca26e6d3abafac3468fdfdf8 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -2494,9 +2494,6 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)
}
}
- /* setup classifier to route priorities to flows */
- cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows);
-
return 0;
err_request_irq:
diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
index 9492d0cf06bbbe227899e9a235f2fe52da3acad6..141523f34d9a9441d47248d24cbd8f3cf0a97bf2 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.c
+++ b/drivers/net/ethernet/ti/cpsw_ale.c
@@ -1695,58 +1695,6 @@ void cpsw_ale_policer_reset(struct cpsw_ale *ale)
cpsw_ale_policer_reset_entry(ale, i);
}
-/* Default classifier is to map 8 user priorities to N receive channels */
-void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
-{
- int pri, idx;
-
- /* Reference:
- * IEEE802.1Q-2014, Standard for Local and metropolitan area networks
- * Table I-2 - Traffic type acronyms
- * Table I-3 - Defining traffic types
- * Section I.4 Traffic types and priority values, states:
- * "0 is thus used both for default priority and for Best Effort, and
- * Background is associated with a priority value of 1. This means
- * that the value 1 effectively communicates a lower priority than 0."
- *
- * In the table below, Priority Code Point (PCP) 0 is assigned
- * to a higher priority thread than PCP 1 wherever possible.
- * The table maps which thread the PCP traffic needs to be
- * sent to for a given number of threads (RX channels). Upper threads
- * have higher priority.
- * e.g. if number of threads is 8 then user priority 0 will map to
- * pri_thread_map[8-1][0] i.e. thread 1
- */
-
- int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */
- { 0, 0, 0, 0, 0, 0, 0, 0, },
- { 0, 0, 0, 0, 1, 1, 1, 1, },
- { 0, 0, 0, 0, 1, 1, 2, 2, },
- { 0, 0, 1, 1, 2, 2, 3, 3, },
- { 0, 0, 1, 1, 2, 2, 3, 4, },
- { 1, 0, 2, 2, 3, 3, 4, 5, },
- { 1, 0, 2, 3, 4, 4, 5, 6, },
- { 1, 0, 2, 3, 4, 5, 6, 7 } };
-
- cpsw_ale_policer_reset(ale);
-
- /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */
- for (pri = 0; pri < 8; pri++) {
- idx = pri;
-
- /* Classifier 'idx' match on priority 'pri' */
- cpsw_ale_policer_read_idx(ale, idx);
- regmap_field_write(ale->fields[POL_PRI_VAL], pri);
- regmap_field_write(ale->fields[POL_PRI_MEN], 1);
- cpsw_ale_policer_write_idx(ale, idx);
-
- /* Map Classifier 'idx' to thread provided by the map */
- cpsw_ale_policer_thread_idx_enable(ale, idx,
- pri_thread_map[num_rx_ch - 1][pri],
- 1);
- }
-}
-
#define HOST_PORT_NUM 0
/* Clear Policer and associated ALE table entries */
diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h
index dbc095397389d36df54a29d46e905f7eeb790e87..5c96147309988a675c3ec6d1361250f927695641 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.h
+++ b/drivers/net/ethernet/ti/cpsw_ale.h
@@ -223,7 +223,6 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask);
void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
bool add);
-void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch);
void cpsw_ale_policer_reset(struct cpsw_ale *ale);
int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx,
struct cpsw_ale_policer_cfg *cfg);
--
2.34.1
prev parent reply other threads:[~2025-10-24 20:46 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-24 20:45 [PATCH net-next v5 0/9] net: ethernet: ti: am65-cpsw: add network flow classification support Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 1/9] net: ethernet: ti: cpsw_ale: Update Policer fields for more ALE size/ports Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 2/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_add_vlan() Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 3/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_vlan_add_modify() Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 4/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_add_ucast() Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 5/9] net: ethernet: ti: cpsw_ale: add cpsw_ale_policer_reset_entry() Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 6/9] net: ethernet: ti: cpsw_ale: add cpsw_ale_policer_set/clr_entry() Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 7/9] net: ethernet: ti: cpsw_ale: add policer save restore for PM sleep Roger Quadros
2025-10-24 20:46 ` [PATCH net-next v5 8/9] net: ethernet: ti: am65-cpsw: add network flow classification support Roger Quadros
2025-10-29 2:08 ` Jakub Kicinski
2025-10-24 20:46 ` Roger Quadros [this message]
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