On Thu, Oct 23, 2025 at 09:49:19PM +0200, Nicolas Frattaroli wrote: > The MediaTek MT8196 SoC includes an M-PHY compatible with the already > existing mt8183 binding. > > However, one omission from the original binding was that all of these > variants may have an optional reset. > > Add the new compatible, and also the resets property, with an example. > > Reviewed-by: AngeloGioacchino Del Regno > Reviewed-by: Peter Wang > Signed-off-by: Nicolas Frattaroli Acked-by: Conor Dooley pw-bot: not-applicable > --- > .../devicetree/bindings/phy/mediatek,ufs-phy.yaml | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml > index 3e62b5d4da61..f414aaa18997 100644 > --- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml > @@ -26,6 +26,7 @@ properties: > - items: > - enum: > - mediatek,mt8195-ufsphy > + - mediatek,mt8196-ufsphy > - const: mediatek,mt8183-ufsphy > - const: mediatek,mt8183-ufsphy > > @@ -42,6 +43,10 @@ properties: > - const: unipro > - const: mp > > + resets: > + items: > + - description: Optional UFS M-PHY reset. > + > "#phy-cells": > const: 0 > > @@ -65,5 +70,16 @@ examples: > clock-names = "unipro", "mp"; > #phy-cells = <0>; > }; > + - | > + #include > + ufs-phy@16800000 { > + compatible = "mediatek,mt8196-ufsphy", "mediatek,mt8183-ufsphy"; > + reg = <0x16800000 0x10000>; > + clocks = <&ufs_ao_clk 3>, > + <&ufs_ao_clk 5>; > + clock-names = "unipro", "mp"; > + resets = <&ufs_ao_clk MT8196_UFSAO_RST0_UFS_MPHY>; > + #phy-cells = <0>; > + }; > > ... > > -- > 2.51.1.dirty >