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From: Huang Shijie <shijie@os.amperecomputing.com>
To: will@kernel.org, mark.rutland@arm.com
Cc: patches@amperecomputing.com, cl@linux.com,
	Shubhang@os.amperecomputing.com,
	linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	Huang Shijie <shijie@os.amperecomputing.com>
Subject: [PATCH] perf: arm-spe: set the correct interval for PMSIRR_EL1
Date: Mon, 27 Oct 2025 10:24:45 +0800	[thread overview]
Message-ID: <20251027022445.892607-1-shijie@os.amperecomputing.com> (raw)

From the spec, the "interval" value for PMSIRR_EL1 is in the [31, 8] bits.
Current code does not set it correctly.

This patch fixes it.

Fixes: d5d9696b03808 ("drivers/perf: Add support for ARMv8.2 Statistical Profiling Extension")
Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
---
 drivers/perf/arm_spe_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index fa50645fedda..d424721b79ee 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -400,7 +400,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *event)
 	arm_spe_event_sanitise_period(event);
 
 	reg |= FIELD_PREP(PMSIRR_EL1_RND, ATTR_CFG_GET_FLD(attr, jitter));
-	reg |= event->hw.sample_period;
+	reg |= FIELD_PREP(PMSIRR_EL1_INTERVAL, event->hw.sample_period);
 
 	return reg;
 }
-- 
2.40.1


             reply	other threads:[~2025-10-27  2:29 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27  2:24 Huang Shijie [this message]
2025-10-27  9:02 ` Shijie Huang

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